Editing Processor register (section)

==Examples==
The following table shows the number of registers in several mainstream CPU architectures. Note that in [[x86]]-compatible processors, the stack pointer (<code>ESP</code>) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.

Although all of the below-listed architectures are different, almost all are in a basic arrangement known as the [[von Neumann architecture]], first proposed by the Hungarian-American [[mathematician]] [[John von Neumann]]. It is also noteworthy that the number of registers on [[GPUs]] is much higher than that on CPUs.

{{sticky header}}
{| class="wikitable sortable  sticky-header" align="left"<!--these are counts of registers, *not* counts of register sets, so do not add entries with counts of register sets or change counts of registers to counts of register sets-->
! Architecture 
! {{nowrap|GPRs/data+address registers}}
! {{nowrap|FP registers}}
! Notes
|-
| [[AT&T Hobbit]] || style="text-align:center;" | {{0|00}}0 || style="text-align:center;" | stack of 7 || All data manipulation instructions work solely within registers, and data must be moved into a register before processing.
|-
| [[Cray-1]]<ref>{{cite web |url=http://www.bitsavers.org/pdf/cray/CRAY-1/2240004C_CRAY-1_Hardware_Reference_Nov77.pdf |title=Cray-1 Computer System Hardware Reference Manual |publisher=[[Cray Research]] |date=November 1977 |access-date=2022-12-23 |url-status=live |archive-url=https://web.archive.org/web/20211107213641/http://www.bitsavers.org/pdf/cray/CRAY-1/2240004C_CRAY-1_Hardware_Reference_Nov77.pdf |archive-date=2021-11-07}}</ref> || style="text-align:center;" | 8 scalar data, 8 address || style="text-align:center;" | 8 scalar, 8 vector
(64 elements)
| Scalar data registers can be integer or floating-point; also 64 scalar scratch-pad T registers and 64 address scratch-pad B registers
|-
| [[4004]]<ref>{{cite web|url=https://bitsavers.computerhistory.org/components/intel/MCS4/MCS-4_UsersManual_Feb73.pdf|url-status=live|title=MCS-4 Micro Computer Set Users Manual|publisher=Intel|date=February 1973|archive-url=https://web.archive.org/web/20050224073529/http://bitsavers.org/pdf/intel/MCS4/MCS-4_UsersManual_Feb73.pdf|archive-date=2005-02-24}}</ref> || style="text-align:center;" | 1 accumulator, 16 others || style="text-align:center;" | {{0|00}}0 ||
|-
| [[8008]]<ref>{{cite web|url=http://bitsavers.informatik.uni-stuttgart.de/components/intel/MCS8/Intel_8008_8-Bit_Parallel_Central_Processing_Unit_Rev4_Nov73.pdf|url-status=live|title=8008 8 Bit Parallel Central Processor Unit Users Manual|publisher=Intel|date=November 1973|access-date=January 23, 2014|archive-url=https://web.archive.org/web/20071004142917/http://bitsavers.org/pdf/intel/MCS8/8008usersManualRev4_Nov73.pdf|archive-date=2007-10-04}}</ref> || style="text-align:center;" | 1 accumulator, 6 others || style="text-align:center;" | {{0|00}}0 || The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load/store/move/increment/decrement instructions and as the source operand in arithmetic instructions.  There is no [[floating-point unit]] (FPU) available.
|-
| [[8080]]<ref>{{cite web|url=https://bitsavers.trailing-edge.com/components/intel/MCS80/98-153B_Intel_8080_Microcomputer_Systems_Users_Manual_197509.pdf|url-status=live|title=Intel 8080 Microcomputer Systems User's Manual|publisher=Intel|date=September 1975|access-date=January 23, 2014|archive-url=https://web.archive.org/web/20101206220948/http://bitsavers.org/pdf/intel/MCS80/98-153B_Intel_8080_Microcomputer_Systems_Users_Manual_197509.pdf|archive-date=2010-12-06}}</ref> || style="text-align:center;" | 1 accumulator, 6 others, 1 stack pointer|| style="text-align:center;" | {{0|00}}0 || The A register is an accumulator to which all arithmetic is done. The register pairs B·C, D·E, and H·L can be used as address registers in some instructions but ALU instructions can only use H·L as a pointer to memory operands. All registers can be used as operands in load/store/move/increment/decrement instructions and as the source operand in arithmetic instructions. Floating-point processors intended for the 8080 were Intel 8231, AMD Am9511, and Intel 8232. They were also readily usable with the [[Z80]] and similar processors.
|-
| [[Z80]]<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1012169 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |page=3 |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1012169 |archive-date=December 26, 2023 |url-status=live}}</ref> || style="text-align:center;" | 17: 1 accumulator, 6 others, alternate set of 1 accumulator and 6 others, 2 index registers, 1 stack pointer|| style="text-align:center;" | {{0|00}}0 || The Z80 expands on the register set of the 8080. The accumulator and flags can be swapped with an alternate. The other 6 registers can be swapped as a group with alternates. The new index registers (IX or IY plus displacement) can generally be substituted for HL.
|-
| [[iAPX432]] || style="text-align:center;" | {{0|00}}0 || style="text-align:center;" | stack of 6 || Stack machine
|-
| [[X86#16-bit|16-bit x86]]<ref>{{cite web|url=https://bitsavers.trailing-edge.com/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf|url-status=live|title=80286 and 80287 Programmer's Reference Manual|publisher=Intel|year=1987|archive-url=https://web.archive.org/web/20150723132516/http://www.textfiles.com/bitsavers/pdf/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf|archive-date=2015-07-23}}</ref> || style="text-align:center;" | {{0|00}}8 || style="text-align:center;" | stack of 8
(if FP present)
| The [[Intel 8086|8086]]/[[Intel 8088|8088]], [[Intel 80186|80186]]/[[Intel 80188|80188]], and [[Intel 80286|80286]] processors, if provided an [[Intel 8087|8087]], [[Intel 80187|80187]] or [[Intel 80287|80287]] co-processor for floating-point operations, support an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without a co-processor, no floating-point registers are supported.
|-
| [[IA-32]]<ref name="intel-x86-manuals">{{cite web|url=http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html|title=Intel 64 and IA-32 Architectures Software Developer Manuals|date=4 December 2019|publisher=Intel}}</ref> || style="text-align:center;" | {{0|00}}8 || style="text-align:center;" | stack of 8 (if FP present),
8 (if SSE/MMX present)
| The [[Intel 80386|80386]] processor requires an [[Intel 80387|80387]] for floating-point operations, later processors had built-in floating-point, with both having an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands. The [[Pentium III]] and later had the [[Streaming SIMD Extensions|SSE]] with additional 128-bit XMM registers.
|-
| [[x86-64]]<ref name="intel-x86-manuals"/><ref>{{cite web|url=https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24592.pdf|title=AMD64 Architecture Programmer's Manual Volume 1: Application Programming|publisher=[[AMD]]|date=October 2013}}</ref> || style="text-align:center;" | {{0|0}}16 || style="text-align:center;" | 16 or 32
(if AVX-512 available)
| FP registers are 128-bit XMM registers, later extended to 256-bit YMM registers with [[Advanced Vector Extensions|AVX/AVX2]] and 512-bit ZMM0–ZMM31 registers with [[AVX-512]].<ref>{{cite web|url=https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf|title=Intel Architecture Instruction Set Extensions and Future Features Programming Reference|publisher=[[Intel]]|date=January 2018}}</ref>
|-
| [[Fairchild F8]]<ref>{{cite book|url=https://datasheets.chipdb.org/Fairchild/F8/F8_prelimUM_Jan75.pdf|title=F8, Preliminary Microprocessor User's Manual|date=January 1975|publisher=Fairchild}}</ref> || style="text-align:center;" | 1 accumulator, 64 scratchpad registers, 1 indirect scratchpad register (ISAR) || {{n/a}} || Instructions can directly reference the first 16 scratchpad registers and can access all scratchpad registers indirectly through the ISAR<ref>{{cite book|url=http://www.bitsavers.org/components/fairchild/f8/F8_Guide_To_Programming_1977.pdf|title=F8 Guide to Programming|publisher=Fairchild MOS Microcomputer Division|year=1977}}</ref>
|-
| [[Geode GX]] || style="text-align:center;" | 1 data, 1 address || style="text-align:center;" | {{0|00}}8 || Geode GX/[[Media GX]]/[[4x86]]/[[cx5x86|5x86]] is the emulation of 486/Pentium compatible processor made by [[Cyrix]]/[[National Semiconductor]]. Like [[Transmeta]], the processor had a translation layer that translated x86 code to native code and executed it.{{citation needed|date=February 2016}} It does not support 128-bit SSE registers, just the 80387 stack of eight 80-bit floating-point registers, and partially supports [[3DNow!]] from AMD. The native processor only contains 1 data and 1 address register for all purposes and it is translated into 4 paths of 32-bit naming registers r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad SRAM for integer operations.{{cn|date=May 2023}}
|-
| [[V.Smile|Sunplus μ'nSP]] || style="text-align:center;" | {{Nowrap|8 (sp, r1-r4, bp, sr, pc)}} || style="text-align:center;" | {{0|00}}0 || A 16-bit processor from the Taiwanese company Sunplus Technology, notably used in VTech's V.Smile line of educational video game consoles, in addition to many plug-in TV games and off-brand consoles starting from the mid-2000s.
|-
| [[Nuon (DVD technology)|VM Labs Nuon]] || style="text-align:center;" | {{0|00}}0 || style="text-align:center;" | {{0|00}}1 || A 32-bit stack machine processor developed by [[VM Labs]] and specialized for multimedia. It can be found on the company's own Nuon DVD player console line and the Game Wave Family Entertainment System from ZaPit games. The design was heavily influenced by Intel's MMX technology; it contained a 128-byte unified stack cache for both vector and scalar instructions. The unified cache can be divided as eight 128-bit vector registers or thirty-two 32-bit SIMD scalar registers through bank renaming; there is no integer register in this architecture.
|-
| [[Nios II]]<ref>{{cite web|url=https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu_nii5v1.pdf|title=Nios II Classic Processor Reference Guide|publisher=[[Altera]]|date=April 2, 2015}}</ref><ref>{{cite web|url=https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf|title=Nios II Gen2 Processor Reference Guide|publisher=Altera|date=April 2, 2015}}</ref> || style="text-align:center;" | {{0|0}}31 || style="text-align:center;" | {{0|00}}8 || Nios II is based on the MIPS IV instruction set{{citation needed|date=February 2016}} and has 31 32-bit GPRs, with register 0 being hardwired to zero, and eight 64-bit floating-point registers{{citation needed|date=February 2016}}
|-
| [[Motorola 6800]]<ref>{{cite web |url=http://www.bitsavers.org/components/motorola/6800/Motorola_M6800_Programming_Reference_Manual_M68PRM(D)_Nov76.pdf |title=M6800 Programming Reference Manual |publisher=[[Motorola]] |date=November 1976|access-date=May 18, 2015|archive-url=https://web.archive.org/web/20111014000206/http://bitsavers.org/pdf/motorola/6800/Motorola_M6800_Programming_Reference_Manual_M68PRM(D)_Nov76.pdf|archive-date=2011-10-14|url-status=live}}</ref> || style="text-align:center;" | 2 accumulators, 1 index, 1 stack || style="text-align:center;" | {{0|00}}0 ||
|-
| [[Motorola 68k]]<ref>{{cite web|url=https://www.nxp.com/docs/en/reference-manual/M68000PRM.pdf|title=Motorola M68000 Family Programmer's Reference Manual|publisher=Motorola|year=1992|access-date=November 10, 2024}}</ref> || style="text-align:center;" | 8 data (d0–d7), 8 address (a0–a7) || style="text-align:center;" | {{0|00}}8
(if FP present)
| Address register 8 (a7) is the stack pointer. 68000, 68010, 68012, 68020, and 68030 require an FPU for floating-point; 68040 had FPU built in. FP registers are 80-bit.
|-
| [[SuperH]] || style="text-align:center;" | {{0|00}}16 || style="text-align:center;" | {{0|00}}6 || 16-bit instruction version (pre-SH-5)
|-
| [[Emotion Engine]]  || style="text-align:center;" | 3(VU0)+ 32(VU1) || style="text-align:center;" | 32 SIMD (integrated in UV1)
+ 2 × 32 Vector 
(dedicated vector co-processor located nearby its GPU)
| The Emotion Engine's main core (VU0) is a heavily modified DSP general core intended for general background tasks and it contains one 64-bit accumulator, two general data registers, and one 32-bit program counter. A modified MIPS&nbsp;III executable core (VU1) is for game data and protocol control, and it contains thirty-two 32-bit general-purpose registers for integer computation and thirty-two 128-bit SIMD registers for storing SIMD instructions, streaming data value and some integer calculation value, and one accumulator register for connecting general floating-point computation to the vector register file on the co-processor. The coprocessor is built via a 32-entry 128-bit vector register file (can only store vector values that pass from the accumulator in the CPU) and no integer registers are built in. Both the vector co-processor (VPU 0/1) and the Emotion Engine's entire main processor module (VU0 + VU1 + VPU0 + VPU1) are built based on a modified MIPS instructions set. The accumulator in this case is not general-purpose but control status.
|-
| {{Anchor|CUDA}}[[CUDA]]<ref>{{cite web|url=https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#compute-capabilities|title=CUDA C Programming Guide|publisher=Nvidia|year=2019|access-date=Jan 9, 2020}}</ref> || style="text-align: center" colspan="2" | configurable, up to 255 per thread || Earlier generations allowed up to 127/63 registers per thread ([[Tesla_(microarchitecture)|Tesla]]/[[Fermi_(microarchitecture)|Fermi]]). The more registers are configured per thread, the fewer threads can run at the same time. Registers are 32 bits wide; [[double-precision floating-point]] numbers and 64-bit pointers therefore require two registers. It additionally has up to 8 predicate registers per thread.<ref>{{cite arXiv|title=Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking |year=2018|eprint=1804.06826|last1=Jia|first1=Zhe|last2=Maggioni|first2=Marco|last3=Staiger|first3=Benjamin|last4=Scarpazza|first4=Daniele P.|class=cs.DC}}</ref>
|-
| [[CDC 6000 series]]<ref>{{cite book|url=http://bitsavers.informatik.uni-stuttgart.de/pdf/cdc/Tom_Hunter_Scans/6000_Series_Computer_Systems_RefMan_Jul65.pdf|title=Control Data 6000 Series Computer Systems, Reference Manual|publisher=Control Data Corporation|date=July 1965}}</ref> || style="text-align:center;" | {{0|0}}16 || style="text-align:center;" | {{0|00}}8 || 8 'A' registers, A0–A7, hold 18-bit addresses; 8 'B' registers, B0–B7, hold 18-bit integer values (with B0 permanently set to zero); 8 'X' registers, X0–X7, hold 60 bits of integer or floating-point data. Seven of the eight 18-bit A registers were coupled to their corresponding X registers: setting any of the A1–A5 registers to a value caused a memory load of the contents of that address into the corresponding X register. Likewise, setting an address into registers A6 or A7 caused a memory store into that location in memory from X6 or X7. (Registers A0 and X0 were not coupled like this).
|-
| [[System/360]],<ref>{{cite book|url=https://bitsavers.trailing-edge.com/pdf/ibm/360/princOps/A22-6821-0_360PrincOps.pdf|title=IBM System/360 Principles of Operation|publisher=IBM|date=}}</ref> [[System/370]],<ref>{{cite book|url=http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf|title=IBM System/370, Principles of Operation|publisher=IBM|date=September 1, 1975 }}</ref> [[System/390]], [[z/Architecture]]<ref>{{cite book|url=https://www.ibm.com/docs/en/SSQ2R2_15.0.0/com.ibm.tpf.toolkit.hlasm.doc/dz9zr006.pdf|title=z/Architecture, Principles of Operation|publisher=IBM|date=2008|edition=Seventh}}</ref> || style="text-align:center;" | {{0|0}}16 || style="text-align:center;" | 4 (if FP present);
16 in G5 and later S/390 models and z/Architecture
| FP was optional in System/360, and always present in S/370 and later. In processors with the Vector Facility, there are 16 vector registers containing a machine-dependent number of 32-bit elements.<ref>{{cite web|url=http://bitsavers.org/pdf/ibm/370/vectorFacility/SA22-7125-3_Vector_Operations_Aug88.pdf|title=IBM Enterprise Systems Architecture/370 and System/370 - Vector Operations|publisher=IBM|id=SA22-7125-3|access-date=May 11, 2020}}</ref> Some registers are assigned a fixed purpose by [[calling convention]]s; for example, register 14 is used for subroutine return addresses and, for [[Executable and Linkable Format|ELF]] ABIs, register 15 is used as a stack pointer. The S/390 G5 processor increased the number of floating-point registers to 16.<ref>{{cite web|url=https://old.hotchips.org/wp-content/uploads/hc_archives/hc10/2_Mon/HC10.S5/HC10.5.1.pdf|title=IBM S/390 G5 Microprocessor}}</ref>
|-
| [[MMIX]]<ref>{{cite web|url=http://mmix.cs.hm.edu|title=MMIX Home Page}}</ref> || style="text-align:center;" | 256 || style="text-align:center;" | 256 || An instruction set designed by [[Donald Knuth]] in the late 1990s for pedagogical purposes.
|-
| [[NS320xx]]<ref>{{cite web|url=http://bitsavers.org/components/national/_dataBooks/1986_National_NS32000_Databook.pdf|title=Series 32000 Databook|publisher=[[National Semiconductor]]|archive-url=https://web.archive.org/web/20171125004028/http://bitsavers.org/components/national/_dataBooks/1986_National_NS32000_dataBook.pdf|archive-date=2017-11-25|url-status=live}}</ref> || style="text-align:center;" | {{0|00}}8 || style="text-align:center;" | {{0|00}}8
(if FP present)
|
|-
| [[Xelerated X10]] || style="text-align:center;" | {{0|00}}1 || style="text-align:center;" | {{0|0}}32 || A 32/40-bit stack machine-based network processor with a modified MIPS instruction set and a 128-bit floating-point unit.{{cn|date=March 2019}}
|-
| [[Parallax Propeller]] || style="text-align:center;" | {{0|00}}0 || style="text-align:center;" | {{0|00}}2 || An eight-core 8/16-bit sliced stack machine controller with a simple logic circuit inside, it has 8 cog counters (cores), each containing three 8/16 bit special control registers with 32 bit x 512 stack RAM. However, it does not contain any general register for integer purposes. Unlike most shadow register files in modern processors and [[multi-core]] systems, all of the stack RAM in cog can be accessed in instruction level, which allows all of these cogs to act as a single general-purpose core if necessary. Floating-point unit is external and it contains two 80-bit vector registers.
|-
| [[Itanium]]<ref>{{cite book|url=https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-3-manual.pdf|title=Intel Itanium Architecture, Software Developer's Manual, Volume 3: Intel Itanium Instruction Set Reference|date=May 2010|publisher=Intel}}</ref> || style="text-align:center;" | 128 || style="text-align:center;" | 128 || And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.
|-
| [[SPARC]]<ref>{{cite book|url=https://www.cs.utexas.edu/~novak/sparcv9.pdf|title=The SPARC Architecture Manual, Version 9|publisher=SPARC International, Inc.|location=Santa Clara, California|editor-last1=Weaver |editor-first1=David L. |editor-last2=Germond |editor-first2=Tom }}</ref> || style="text-align:center;" | {{0|0}}31 || style="text-align:center;" | {{0|0}}32 || Global register 0 is hardwired to 0. Uses [[register window]]s.
|-
| [[IBM POWER Instruction Set Architecture|IBM POWER]] || style="text-align:center;" | {{0|0}}32 || style="text-align:center;" | {{0|0}}32 || Also included are a link register, a count register, and a multiply quotient (MQ) register.
|-
| [[PowerPC]]/[[Power ISA]]<ref>{{cite book|url=https://wiki.raptorcs.com/w/images/d/d3/OPF_PowerISA_v3.1B.pdf|title=Power ISA Version 3.1B|date=September 14, 2021|publisher=OpenPOWER Foundation}}</ref> || style="text-align:center;" | {{0|0}}32 || style="text-align:center;" | {{0|0}}32 || Also included are a link register and a count register. Processors supporting the [[AltiVec|Vector facility]] also have 32 128-bit vector registers.
|-
| [[Blackfin]]<ref>{{cite book|url=https://www.analog.com/media/en/dsp-documentation/processor-manuals/Blackfin_pgr_rev2.2.pdf|title=Blackfin Processor, Programming Reference, Revision 2.2|date=February 2013|publisher=Analog Devices}}</ref> || style="text-align:center;" | 8 data, 2 accumulator, 6 address || style="text-align:center;" | {{0|00}}0 || Also included are a stack pointer and a frame pointer. Additional registers are used to implement zero-overhead loops and circular buffer DAGs (data address generators).
|-
| [[IBM Cell#Synergistic Processing Elements (SPE)|IBM Cell SPE]] || style="text-align: center" colspan="2"| 128 || 128 general purpose registers, which can hold integer, address, or floating-point values<ref>{{cite web|url=https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/76CA6C7304210F3987257060006F2C44/$file/SPU_ISA_v1.2_27Jan2007_pub.pdf|title=Synergistic Processor Unit Instruction Set Architecture Version 1.2|publisher=IBM|date=January 27, 2007}}</ref>
|-
| [[DEC PDP-10|PDP-10]] || style="text-align: center" colspan="2"| {{0|0}}16 || All of the registers may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. [[Magnetic-core memory|core]]) memory locations 0–15; a hardware option called "fast memory" implemented the registers as separate ICs, and references to memory locations 0–15 referred to the IC registers.  Later models implemented the registers as "fast memory" and continued to make memory locations 0–15 refer to them. Movement instructions take ''(register, memory)'' operands: {{code|MOVE 1,2}} is register-register, and {{code|MOVE 1,1000}} is memory-to-register.
|-
| [[DEC PDP-11|PDP-11]] || style="text-align:center;" | {{0|00}}7 || style="text-align:center;" | {{0|00}}6
(if FPP present)
| R7 is the program counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.
|-
| [[DEC VAX|VAX]]<ref>{{cite book|url=https://bitsavers.trailing-edge.com/pdf/dec/vax/archSpec/EY-3459E-DP_VAX_Architecture_Reference_Manual_1987.pdf|title=VAX Architecture, Reference Manual|editor-first1=Timothy E.|editor-last1=Leonard|publisher=DEC books|date= 1987}}</ref> || style="text-align: center" colspan="2"| {{0|0}}16 || The general purpose registers are used for floating-point values as well. Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.
|-
| [[DEC Alpha|Alpha]]<ref>{{cite book|url=https://download.majix.org/dec/alpha_arch_ref.pdf|title=Alpha Architecture Reference Manual|edition=Fourth|publisher=Compaq Computer Corporation|date=January 2002}}</ref> || style="text-align:center;" | {{0|0}}31 || style="text-align:center;" | {{0|0}}31 || Registers R31 (integer) and F31 (floating-point) are hardwired to zero.
|-
| [[MOS Technology 6502|6502]] || style="text-align:center;" | 1 accumulator, 2 index, 1 stack|| style="text-align:center;" | {{0|00}}0 ||The A (accumulator) register is the destination for all ALU operations.  X and Y are indirect and direct index registers (respectively). The S (stack pointer) register points to the top of stack.
|-
| [[65C816|W65C816S]] || style="text-align:center;" | {{0|00}}1 || style="text-align:center;" | {{0|00}}0 || 65c816 is the 16-bit successor of the 6502. X, Y, and D (Direct Page register) are condition registers and SP register are specific index only. Main accumulator extended to 16-bit (C)<ref>{{Cite web|url=https://wiki.superfamicom.org/learning-65816-assembly#toc-2|title=Learning 65816 Assembly|website=Super Famicom Development Wiki|access-date=14 November 2019}}</ref> while keeping 8-bit (A) for compatibility and main registers can now address up to 24-bit (16-bit wide data instruction/24-bit memory address).
|-
| [[Media-embedded processor|MeP]] || style="text-align:center;" | {{0|00}}4 || style="text-align:center;" | {{0|00}}8 || Media-embedded processor was a 32-bit processor developed by [[Toshiba]] with a modded 8080 instruction set. Only the A, B, C, and D registers are available through all modes (8/16/32-bit). It is incompatible with x86; however, it contains an 80-bit floating-point unit that is x87-compatible.
|-
| [[PIC microcontroller]] || style="text-align:center;" | {{0|00}}1 || style="text-align:center;" | {{0|00}}0 || The base PIC architecture has no mechanism to index memory.
|-
| [[Atmel AVR|AVR microcontroller]] || style="text-align:center;" | {{0|0}}32 || style="text-align:center;" | {{0|00}}0 ||
|-
| [[ARM architecture|ARM]] 32-bit (ARM/A32, Thumb-2/T32) || style="text-align:center;" | {{0|0}}14 || style="text-align:center;" | Varies
(up to 32)
| r15 is the program counter, and not usable as a general purpose register; r13 is the stack pointer; r8–r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing,<ref>{{cite web|url=http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf|title=Procedure Call Standard for the ARM Architecture|publisher=[[ARM Holdings]]|date=30 November 2013|access-date=27 May 2013}}</ref> and used upper bits of the program counter (r15) for status flags, making that register 32-bit.
|-
| [[ARM architecture|ARM]] 32-bit (Thumb) || style="text-align:center;" | {{0|00}}8 || style="text-align:center;" | {{0|0}}16 || Version 1 of Thumb, which only supported access to registers r0 through r7<ref>{{cite web|url=https://developer.arm.com/docs/ddi0210/latest/programmers-model/registers/the-thumb-state-register-set|title=2.6.2. The Thumb-state register set|work=ARM7TDMI Technical Reference Manual|publisher=[[ARM Holdings]]}}</ref>
|-
| [[ARM architecture|ARM]] 64-bit (A64) <ref>{{cite book|url=https://student.cs.uwaterloo.ca/~cs452/docs/rpi4b/ISA_A64_xml_v88A-2021-12_OPT.pdf|title=Arm A64 Instruction Set Architecture, Armv8, for Armv8-A architecture profile|publisher=Arm|date=2021}}</ref>|| style="text-align:center;" | {{0|0}}31 || style="text-align:center;" | {{0|0}}32 || Register r31 is the stack pointer or hardwired to 0, depending on the context.
|-
| [[MIPS architecture|MIPS]]<ref>{{cite book|url=https://www.ece.lsu.edu/ee4720/mips64v2.pdf|title=MIPS64 Architecture For Programmers, Volume II: The MIPS64 Instruction Set|date=March 12, 2001|publisher=RISC-V Foundation|access-date=October 6, 2024}}</ref> || style="text-align:center;" | {{0|0}}31 || style="text-align:center;" | {{0|0}}32 || Integer register 0 is hardwired to 0.
|-
| [[RISC-V]]<ref>{{cite book|url=https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf|title=The RISC-V, Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2|publisher=RISC-V Foundation|date=May 2017|editor-last1=Waterman|editor-first1=Andrew|editor-last2=Asanovi|editor-first2=Krste }}</ref> || style="text-align:center;" | {{0|0}}31 || style="text-align:center;" | {{0|0}}32 || Integer register 0 is hardwired to 0. The RV32E variant, intended for systems with very limited resources, has 15 integer registers.
|-
| [[Adapteva|Epiphany]] || style="text-align: center" colspan="2" | 64 (per core)<ref>{{cite web|url=http://adapteva.com/docs/epiphany_arch_ref.pdf|title=Epiphany Architecture Reference}}</ref> || Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.
|}

{{Clear}}