Editing Programmable Array Logic (section)

==PAL architecture==
[[File:Programmable Logic Device.svg|thumb|350px|The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as ''product terms'', are ORed together to form a ''sum-of-products'' logic array.]]
The PAL architecture consists of two main components: a logic plane and output logic macrocells.

===Programmable logic plane===
The programmable logic plane is a [[programmable read-only memory]] (PROM) array that allows the signals present on the device pins, or the logical complements of those signals, to be routed to output logic macrocells.

PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "[[disjunctive normal form|sum-of-products]]" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.

===Output logic===
The early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be registered or combinational. Members of the PAL family were available with various output structures called "[[output logic macrocell]]s" or OLMCs. Prior to the introduction of the "V" (for "variable") series, the types of OLMCs available in each PAL were fixed at the time of manufacture. (The PAL16L8 had 8 combinational outputs, and the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2 combinational outputs, while the PAL16R4 had 4 of each.) Each output could have up to 8 product terms (effectively AND gates); however, the combinational outputs used one of the terms to control a bidirectional output buffer. There were other combinations that had fewer outputs with more product terms per output and were available with active high outputs ("H" series).<ref name="mmi3" />{{rp|1&ndash;14}} The "X" series of devices had an XOR gate before the register.<ref name="mmi3">{{cite book |title=PAL Programmable Array Logic Handbook |edition=3rd |last1=Birkner |first1=John M. |last2=Coli |first2=Vincent J. |publisher=Monolithic Memories, Inc. |year=1983}}</ref>{{rp|1&ndash;9}} There were also similar 24-pin versions of these PALs.

This fixed output structure often frustrated designers attempting to optimize the utility of PAL devices because output structures of different types were often required by their applications. (For example, one could not get 5 registered outputs with 3 active high combinational outputs.) So, in June 1983 [[AMD]] introduced the 22V10, a 24-pin device with 10 output logic macrocells.<ref name="22V10 Data Sheet">{{Cite book |date=June 1983 |title=AmPAL 22V10 Advanced Information |publication-place=Sunnyvale CA |publisher=Advanced Micro Devices |id=04126A-PLP}} Note: This is the data sheet published by AMD when the AmPAL 22V10 was introduced.</ref> Each macrocell could be configured by the user to be combinational or registered, active high or active low. The number of product terms allocated to an output varied from 8 to 16. This one device could replace all of the 24-pin fixed function PAL devices. Members of the PAL "V" ("variable") series included the PAL16V8, PAL20V8 and PAL22V10.

<gallery class= "center">
PAL Block Diagram.jpg|PAL 16R4 Block Diagram
22V10 Block Diagram.jpg|AMD 22V10 Block Diagram
AMD 22V10 Macrocell.jpg|AMD 22V10 Output Macrocell
</gallery>