Editing SIMM (section)

==72-pin SIMMs==
[[Image:Edoram.jpg|thumb|72-pin EDO DRAM SIMM]]
Standard sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB (the standard also defines 3.3&nbsp;V modules with additional address lines and up to 2&nbsp;GB)

With 12 address lines, which can provide a total of 24 address bits, two ranks of chips, and 32-bit data output, the absolute maximum capacity is 2<sup>27</sup> = 128&nbsp;MB.<!-- (32 * 2**(14*2)) / (8*1048576) http://www.pjrc.com/mp3/simm/datasheet.html -->
<!-- Extensive googling has failed to turn up evidence of a 256 MB SIMM.  You can search for it, but in every instance it's a multi-SIMM kit (e.g. 2x128 MB, 4x64 MB) or a mislabeled DIMM such as Sun X7005A 512 MB Memory Kit (picture has two notches, not 1).  Note that in the era when memory meant SIMM, people tended to mis-name the similar-appearing DIMMs in casual conversation. -->

{|class="wikitable"
|+5 V 72-pin SIMM
!Pin #!!Name!!Signal description
|rowspan=37|
!Pin #!!Name!!Signal description
|-
|1||V<sub>SS</sub>||Ground
|37||MDP1<sup>*</sup>||Data parity 1 (MD8..15)
|-
|2||MD0||Data 0
|38||MDP3<sup>*</sup>||Data parity 3 (MD24..31)
|-
|3||MD16||Data 16
|39||V<sub>SS</sub>||Ground
|-
|4||MD1||Data 1
|40||/CAS0||Column address strobe 0
|-
|5||MD17||Data 17
|41||/CAS2||Column address strobe 2
|-
|6||MD2||Data 2
|42||/CAS3||Column address strobe 3
|-
|7||MD18||Data 18
|43||/CAS1||Column address strobe 1
|-
|8||MD3||Data 3
|44||/RAS0||Row address strobe 0
|-
|9||MD19||Data 19
|45||/RAS1<sup>†</sup>||Row address strobe 1
|-
|10||V<sub>CC</sub>||+5 VDC
|46||NC||Not connected <!-- JEDEC says /G (/OE, output enable)on 3.3V SIMMs, but I don't see that:
http://www.icwic.cn/icwic/data/pdf/cd/cd012/140346.pdf
*{{cite web|url=http://doc.chipfind.ru/hanbit/hmd4m32m2ve.htm|title=HMD4M32M2VE (Hanbit) - 16mbyte(4mx32) Dram Simm Edo Mode, 4k Refresh, 3.3v|publisher=doc.chipfind.ru|accessdate=2014-02-11}}
-->
|-
|11||NU [PD5<sup>#</sup>]||Not used [presence detect 5 (3v3)]
|47||/WE||Read/write enable
|-
|12||MA0||Address 0
|48||NC [/ECC<sup>#</sup>]||Not connected [ECC presence (if grounded) (3v3)]
|-
|13||MA1||Address 1
|49||MD8||Data 8
|-
|14||MA2||Address 2
|50||MD24||Data 24
|-
|15||MA3||Address 3
|51||MD9||Data 9
|-
|16||MA4||Address 4
|52||MD25||Data 25
|-
|17||MA5||Address 5
|53||MD10||Data 10
|-
|18||MA6||Address 6
|54||MD26||Data 26
|-
|19||MA10||Address 10
|55||MD11||Data 11
|-
|20||MD4||Data 4
|56||MD27||Data 27
|-
|21||MD20||Data 20
|57||MD12||Data 12
|-
|22||MD5||Data 5
|58||MD28||Data 28
|-
|23||MD21||Data 21
|59||V<sub>CC</sub>||+5 VDC
|-
|24||MD6||Data 6
|60||MD29||Data 29
|-
|25||MD22||Data 22
|61||MD13||Data 13
|-
|26||MD7||Data 7
|62||MD30||Data 30
|-
|27||MD23||Data 23
|63||MD14||Data 14
|-
|28||MA7||Address 7
|64||MD31||Data 31
|-
|29||MA11||Address 11
|65||MD15||Data 15
|-
|30||V<sub>CC</sub>||+5 VDC
|66||NC [/EDO<sup>#</sup>]||Not connected [EDO presence (if grounded) (3v3)]
|-
|31||MA8||Address 8
|67||PD1<sup>x</sup>||Presence detect 1
|-
|32||MA9||Address 9
|68||PD2<sup>x</sup>||Presence detect 2
|-
|33||/RAS3<sup>†</sup>||Row address strobe 3
|69||PD3<sup>x</sup>||Presence detect 3
|-
|34||/RAS2||Row Address Strobe 2
|70||PD4<sup>x</sup>||Presence detect 4
|-
|35||MDP2<sup>*</sup>||Data parity 2 (MD16..23)
|71||NC [PD (ref)<sup>#</sup>]||Not connected [presence detect (ref) (3v3)]
|-
|36||MDP0<sup>*</sup>||Data parity 0 (MD0..7)
|72||V<sub>SS</sub>||Ground
|}
<sup>*</sup> Pins 35, 36, 37 and 38 are not connected on non-parity SIMMs.<ref>[http://www.jedec.org/sites/default/files/docs/4_04_02R8.PDF JEDEC Standard No. 21-C, Section 4.4.2] "72 pin SIMM DRAM Module Family".</ref><br/>
<sup>†</sup> /RAS1 and /RAS3 are only used on two-rank SIMMS: 2, 8, 32, and 128 MB.<br/>
<sup>#</sup> These lines are only defined on 3.3 V modules.<br/>
<sup>x</sup> Presence-detect signals are detailed in JEDEC standard.