Editing Silicon on insulator (section)

==Manufacture of SOI wafers==
[[File:SIMOX processing schematic.svg|thumb|300px|SIMOX process]]
[[File:Smart Cut SOI Wafer Manufacturing Schema.svg|thumb|300px|Smart Cut process]]
{{chem|SiO|2}}-based SOI wafers can be produced by several methods:
*''[[SIMOX]]'' - '''S'''eparation by '''IM'''plantation of '''OX'''ygen &ndash; uses an oxygen [[ion implantation|ion beam implantation]] process followed by high temperature annealing to create a buried {{chem|SiO|2}} layer.<ref>{{cite patent |inventor=Atsushi Ogura |title=Method of fabricating SOI substrate |country=US  |number=5888297 |url= |gdate=1999-03-30}}</ref><ref>{{cite patent |inventor=Hiroshi Fujioka |title=Method of manufacturing semiconductor on insulator |country=US |number=5061642 |url= |gdate=1991-10-29}}</ref>
*[[Wafer bonding]]<ref>{{cite book |first1=Q.-Y. |last1=Tong |first2=U. |last2=Gösele |title=SemiConductor Wafer Bonding: Science and Technology |publisher=Wiley |date=1998 |isbn=978-0-471-57481-1 |pages= |url=}}</ref><ref>{{cite patent |inventor-first=George |inventor-last=Bajor |invent2=et al. |title=Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor |country=US |number=4771016 |url= |gdate=1988-09-13}}</ref> &ndash; the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
**One prominent example of a wafer bonding process is the ''[[Smart Cut]]'' method developed by the French firm [[Soitec]] which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
**''NanoCleave'' is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and [[silicon-germanium]] alloy.<ref>{{cite web|url=http://www.sigen.com/|title=SIGEN.COM|website=www.sigen.com|access-date=22 April 2018}}</ref>
**''ELTRAN'' is a technology developed by Canon which is based on porous silicon and water cut.<ref>{{cite web |last1=Yonehara |first1=T |last2=Sakaguchi |first2=K.|url=http://www.jsapi.jsap.or.jp/Pdf/Number04/CuttingEdge2.pdf |title=ELTRAN® Novel SOI Wafer Technology |work=Cutting Edge 2 |publisher=Canon}}</ref>
*Seed methods<ref>{{cite patent |country=US |number=5417180}}</ref> - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

An exhaustive review of these various manufacturing processes may be found in reference<ref name="celler"/>