Editing Synchronous dynamic random-access memory (section)

== Control signals ==
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly [[Logic level|active low]], which are sampled on the rising edge of the clock:
* '''CKE''' clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.
* '''{{overline|CS}}''' chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
* '''DQM''' data mask. (The letter ''Q'' appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.

=== Command signals ===
* '''{{overline|RAS}}''', row address strobe. Despite the name, this is ''not'' a strobe, but rather simply a command bit. Along with {{overline|CAS}} and {{overline|WE}}, this selects one of eight commands.
* '''{{overline|CAS}}''', column address strobe. This is also not a strobe, rather a command bit. Along with {{overline|RAS}} and {{overline|WE}}, this selects one of eight commands.
* '''{{overline|WE}}''', write enable. Along with {{overline|RAS}} and {{overline|CAS}}, this selects one of eight commands. It generally distinguishes read-like commands from write-like commands.

=== Bank selection (BAn) ===
SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.

=== Addressing (A10/An) ===
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.

=== Commands ===
The SDR SDRAM commands are defined as follows:

{| class="wikitable" style="text-align:center"
! {{overline|CS}} || {{overline|RAS}} || {{overline|CAS}} || {{overline|WE}} || BA''n'' || A10 || A''n'' || Command
|-
|bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x  ||bgcolor=lightgrey| x  ||bgcolor=lightgrey| x ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Command inhibit (no operation)
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| No operation
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Burst terminate: stop a burst read or burst write in progress
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   || bank    ||bgcolor=#ccffcc| L   || column ||align="left"| Read: read a burst of data from the currently active row
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   || bank    ||bgcolor=#ffcccc| H   || column ||align="left"| Read with auto precharge: as above, and precharge (close row) when done
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ccffcc| L   || column ||align="left"| Write: write a burst of data to the currently active row
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ffcccc| H   || column ||align="left"| Write with auto precharge: as above, and precharge (close row) when done
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H   || bank  ||colspan="2"| row ||align="left"| Active (activate): open a row for read and write commands
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x      ||align="left"| Precharge: deactivate (close) the current row of selected bank
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x       ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x      ||align="left"| Precharge all: deactivate (close) the current row of all banks
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged.
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || 0 0  ||colspan="2"| mode ||align="left"| Load mode register: A0 through A9 are loaded to configure the DRAM chip.<br/>The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)
|}

All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being:
* Additional address bits to support larger devices
* Additional bank select bits
* Wider mode registers (DDR2 and up use 13 bits, A0–A12)
* Additional extended mode registers (selected by the bank address bits)
* DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"
* DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer
* [[DDR4#Command encoding|DDR4 changes the encoding]] of the activate command. A new signal {{overline|ACT}} controls it, during which the other control lines are used as row address bits 16, 15 and 14. When {{overline|ACT}} is high, other commands are the same as above.