Editing System bus (section)

==Dual Independent Bus==
[[Intel]] has used the term ''Dual Independent Bus'' (DIB) for two different purposes. The first one came when Intel changed from a single [[local bus]] to the DIB, using the external [[front-side bus]] to the main system [[Computer data storage|memory]] and I/O devices, and the internal [[back-side bus]] to the L2 [[CPU cache]]. This was introduced in the [[Pentium Pro]] in 1995.<ref>[https://www.intel.com/pressroom/archive/releases/1997/CN040997.HTM Intel's CEO Reveals New Bus Architecture To Be Implemented In Upcoming Pentium® II Microprocessor]</ref><ref>{{cite web |title= Introduction to Intel Architecture: The Basics |author= Todd Langley and Rob Kowalczyk |date= January 2009 |url= ftp://download.intel.com/design/intarch/PAPERS/321087.pdf |publisher= Intel Corporation |work= White paper |archive-url= https://web.archive.org/web/20090712091351/http://download.intel.com:80/design/intarch/papers/321087.pdf |archive-date= 2009-07-12 |url-status= dead |access-date= May 25, 2011 }}</ref><ref>{{cite magazine |title=Accelerated Graphics Port |magazine=[[Next Generation (magazine)|Next Generation]]|issue=37|publisher=[[Imagine Media]] |date=January 1998 |pages=94–96}}</ref>

In 2005 and 2006 Intel introduced the 8500 and 5000 chipsets, where DIB referred to the two [[front-side bus]]es on a chipset, which doubles the system bandwidth compared to having just one FSB shared by all the CPUs. However, the information needed to guarantee the [[cache coherence]] of shared data located in different caches have to be sent in broadcast (snooped) to check the other FSB's CPUs' cache state, reducing the available bandwidth. To reduce the coherency traffic, a [[snoop filter]] was included in the higher-end chipsets, in order to have cache state information available on-chipset. In 2007 Intel extended the idea of multiple buses in the 7300 chipset with four independent FSBs, calling it ''dedicated high-speed interconnects'' (DHSI).<ref>[https://www.intel.com/content/www/us/en/io/quickpath-technology/quick-path-interconnect-introduction-paper.html An Introduction to the Intel® QuickPath Interconnect], Figures 4 and 5.</ref> 

The system bus approach is obsolete in the modern personal and server computers, which instead use higher-performance interconnection technologies such as [[HyperTransport]] and [[Intel QuickPath Interconnect]], while the system bus architecture continued to be used on simpler embedded microprocessors.
The systems bus can even be internal to a single integrated circuit, producing a [[system-on-a-chip]]. Examples of on-chip bus include [[Advanced Microcontroller Bus Architecture|AMBA]], [[CoreConnect]], [[Wishbone (computer bus)|Wishbone]], and modified versions of [[PCI bus|PCI]] or [[PCIe]].<ref>{{cite web |title= OpenCores SoC Bus Review |author= Rudolf Usselmann |date= January 9, 2001 |url= http://opencores.org/cdn/downloads/soc_bus_comparison.pdf |access-date= May 30, 2011 }}</ref>