Editing Toffoli gate (section)

== Hardware description ==

The classical Toffoli gate implemented in the hardware description language [[Verilog]]:
<syntaxhighlight lang="verilog">
module toffoli_gate (
 input u1, input u2, input in,
 output v1, output v2, output out);
always @(*) begin
    v1 = u1;
    v2 = u2;
    out = in ^ (u1 && u2);
end
endmodule
</syntaxhighlight>