Editing Translation lookaside buffer (section)

==Multiple TLBs==
Similar to caches, TLBs may have multiple levels. CPUs can be (and nowadays usually are) built with multiple TLBs, for example a small L1 TLB (potentially fully associative) that is extremely fast, and a larger L2 TLB that is somewhat slower. When instruction-TLB (ITLB) and data-TLB (DTLB) are used, a CPU can have three (ITLB1, DTLB1, TLB2) or four TLBs.

For instance, [[Intel]]'s [[Nehalem (microarchitecture)|Nehalem]] microarchitecture has a four-way set associative L1 DTLB with 64 entries for 4&nbsp;KiB pages and 32 entries for 2/4&nbsp;MiB pages, an L1 ITLB with 128 entries for 4&nbsp;KiB pages using four-way associativity and 14 fully associative entries for 2/4&nbsp;MiB pages (both parts of the ITLB divided statically between two threads)<ref>{{cite web|url=http://www.realworldtech.com/page.cfm?ArticleID=RWT040208182719&p=4|publisher=Real World Technologies|title=Inside Nehalem: Intel's Future Processor and System|date=2 April 2008 }}</ref> and a unified 512-entry L2 TLB for 4&nbsp;KiB pages,<ref>{{cite web|url=http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-11.html|publisher=[[Tom's Hardware]]|title=Intel Core i7 (Nehalem): Architecture By AMD?|access-date=24 November 2010|date=14 October 2008}}</ref> both 4-way associative.<ref>{{cite web|url=http://www.realworldtech.com/page.cfm?ArticleID=RWT040208182719&p=8|publisher=Real World Technologies|title=Inside Nehalem: Intel's Future Processor and System|date=2 April 2008 |access-date=24 November 2010}}</ref>

Some TLBs may have separate sections for small pages and huge pages. For example, Intel [[Skylake (microarchitecture)|Skylake]] microarchitecture separates the TLB entries for 1&nbsp;GiB pages from those for 4&nbsp;KiB/2&nbsp;MiB pages.<ref>{{Cite web |last1=Srinivas |first1=Suresh |last2=Pawar |first2=Uttam |last3=Aribuki |first3=Dunni |last4=Manciu |first4=Catalin |last5=Schulhof |first5=Gabriel |last6=Prasad |first6=Aravinda |date=1 November 2019 |title=Runtime Performance Optimization Blueprint: Intel® Architecture Optimization with Large Code Pages |url=https://www.intel.com/content/www/us/en/developer/articles/technical/runtime-performance-optimization-blueprint-intel-architecture-optimization-with-large-code.html |access-date=22 October 2022}}</ref>