Editing VIA C7 (section)

=== Esther ===
The '''Esther''' (C5J) is the next evolution step of the Nehemiah+ (C5P) core of the [[VIA C3]] line-up.

New Features of this core include:
* Average power consumption of less than 1 watt.
* 2&nbsp;GHz operation and a [[Thermal Design Power|TDP]] of 20 watts.
* L2 cache increased from 64k to 128k, with associativity increased from 16-way set associative in C3 to 32-way set associative in C7.
* VIA has stated<ref>{{cite web | author = Shilov, Anton | title = VIA Denies Intel Pentium M Bus Licensing | publisher = X-bit labs | url = http://www.xbitlabs.com/news/mobile/display/20050518045045.html | access-date = 2007-04-23 | url-status = dead | archive-url = https://web.archive.org/web/20070513120849/http://www.xbitlabs.com/news/mobile/display/20050518045045.html | archive-date = 2007-05-13 }}</ref> the C7 bus is physically based upon the Pentium-M 479-pin packaging, but uses the proprietary VIA V4 bus for electrical signalling, instead of Intel’s AGTL+ Quad Pumped Bus, avoiding legal infringement.
* "Twin Turbo" technology, which consists of dual [[Phase-locked loop|PLLs]], one set at a high clock speed, and the other set at a lower speed. This allows the processor's clock frequency to be adjusted in a single processor cycle. Lower switching latency means that more aggressive regulation can be employed.
* Support for [[SSE2]] and [[SSE3]] extended instructions.
* [[NX bit]] in [[Physical Address Extension|PAE]] mode that prevents [[buffer overflow]] software bugs from being exploitable by viruses or attackers.
* Hardware support for [[SHA-1]] and [[SHA-256]] hashing.
* Hardware based "[[Montgomery reduction|Montgomery multiplier]]" supporting key sizes up to 32K for [[public-key cryptography]].