Editing Verilog (section)

===Beginning===
Verilog was created by [[Prabhu Goel]], [[Phil Moorby]] and Chi-Lai Huang between late 1983 and early 1984.<ref>{{cite magazine |title=Verilog's inventor nabs EDA's Kaufman award |date= 7 November 2005 |magazine=EE Times |url=http://www.eetimes.com/document.asp?doc_id=1157349}}</ref> Chi-Lai Huang had earlier worked on a hardware description LALSD, a language developed by Professor [[S.Y.H. Su]], for his PhD work.<ref>{{cite book |first1=Chi-Lai |last1=Huang |first2=S.Y.H. |last2=Su |chapter=Approaches for Computer-Aided Logic System Design Using Hardware Description Language |title=Proceedings of International Computer Symposium 1980, Taipei, Taiwan, December 1980 |pages=772–79O |oclc=696254754}}</ref> The rights holder for this process, at the time proprietary, was "Automated Integrated Design Systems" (later renamed to [[Gateway Design Automation]] in 1985). Gateway Design Automation was purchased by [[Cadence Design Systems]] in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog [[logic simulator]]s) for the next decade. Originally, Verilog was only intended to describe and allow simulation; the automated synthesis of subsets of the language to physically realizable structures (gates etc.) was developed after the language had achieved widespread usage.

Verilog is a portmanteau of the words "verification" and "logic".<ref>{{cite web |title=Oral History of Philip Raymond "Phil" Moorby |date=22 April 2013 |publisher=Computer History Museum |url=http://archive.computerhistory.org/resources/access/text/2013/11/102746653-05-01-acc.pdf |pages=23–25}}</ref>