Editing X86 virtualization (section)

=== Central processing unit ===

==== Virtual 8086 mode ====
{{Main|Virtual 8086 mode}}

Because the [[Intel 80286]] could not run concurrent DOS applications well by itself in protected mode, Intel introduced the [[virtual 8086 mode]] in their [[Intel 80386|80386]] chip, which offered virtualized 8086 processors on the 386 and later chips. Hardware support for virtualizing the protected mode itself, however, became available 20 years later.<ref>{{cite web |last=Yager |first=Tom |url=http://www.infoworld.com/article/2664741/computer-hardware/sending-software-to-do-hardware-s-job.html |title=Sending software to do hardware's job &#124; Hardware - InfoWorld |publisher=Images.infoworld.com |date=2004-11-05 |access-date=2014-01-08 |url-status=live |archive-url=https://web.archive.org/web/20141018133427/http://www.infoworld.com/article/2664741/computer-hardware/sending-software-to-do-hardware-s-job.html |archive-date=2014-10-18}}</ref>

==== {{Anchor|AMD-V}}AMD virtualization (AMD-V) ====
[[File:AMD Phenom die equalized.png|thumb|[[AMD Phenom]] die]]

AMD developed its first generation virtualization extensions under the code name "Pacifica", and initially published them as AMD Secure Virtual Machine (SVM),<ref>{{cite web |url=http://www.mimuw.edu.pl/~vincent/lecture6/sources/amd-pacifica-specification.pdf |title=33047_SecureVirtualMachineManual_3-0.book |access-date=2010-05-02 |url-status=live |archive-url=https://web.archive.org/web/20120305061511/http://www.mimuw.edu.pl/~vincent/lecture6/sources/amd-pacifica-specification.pdf |archive-date=2012-03-05}}</ref> but later marketed them under the trademark ''AMD Virtualization'', abbreviated ''AMD-V''.

On May 23, 2006, AMD released the Athlon 64 ([[List of AMD Athlon 64 microprocessors#"Orleans" (F2 & F3, 90 nm)|"Orleans"]]), the Athlon 64 X2 ([[List of AMD Athlon 64 microprocessors#"Windsor" (F2 & F3, 90 nm)|"Windsor"]]) and the Athlon 64 FX ([[List of AMD Athlon 64 microprocessors#"Windsor" (F2, 90 nm)|"Windsor"]]) as the first AMD processors to support this technology.

AMD-V capability also features on the [[Athlon 64]] and [[Athlon 64 X2]] family of processors with revisions "F" or "G" on [[socket AM2]], [[AMD Turion#Turion 64 X2|Turion 64 X2]], and [[Opteron]] 2nd generation<ref>{{cite web |url=http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_8796_8806~111165,00.html#111166 |title=What are the main differences between Second-Generation AMD Opteron processors and first-generation AMD Opteron processors? |website=amd.com |access-date=2012-02-04 |url-status=dead |archive-url=https://web.archive.org/web/20090415210555/http://www.amd.com/us-en/Processors/ProductInformation/0%2C%2C30_118_8796_8806~111165%2C00.html#111166 |archive-date=April 15, 2009}}</ref> and third-generation,<ref>{{cite web |url=http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_8796_8806~119722,00.html#119726 |title=What virtualization enhancements do Quad-Core AMD Opteron processors feature? |website=amd.com |access-date=2012-02-04 |url-status=dead |archive-url=https://web.archive.org/web/20090416073603/http://www.amd.com/us-en/Processors/ProductInformation/0%2C%2C30_118_8796_8806~119722%2C00.html#119726 |archive-date=April 16, 2009}}</ref> [[AMD Phenom|Phenom]] and [[Phenom II]] processors. The [[AMD Accelerated Processing Unit|APU Fusion]] processors support AMD-V. AMD-V is not supported by any Socket 939 processors. The only [[Sempron]] processors which support it are APUs and [[List of AMD Sempron microprocessors#"Huron" (65&nbsp;nm, Low power)|Huron]], [[List of AMD Sempron microprocessors#"Regor" (Socket AM3, Dual-core, C3, 45 nm)|Regor]], [[List of AMD Sempron microprocessors#"Sargas" (Socket AM3, Single-core, C2 & C3, 45&nbsp;nm)|Sargas]] desktop CPUs.

AMD Opteron CPUs beginning with the Family 0x10 Barcelona line, and Phenom II CPUs, support a second generation hardware virtualization technology called [[Rapid Virtualization Indexing]] (formerly known as Nested Page Tables during its development), later adopted by Intel as [[Extended Page Table]]s (EPT).

As of 2019, all [[Zen (microarchitecture)|Zen]]-based AMD processors support AMD-V.

The [[CPU flag (x86)|CPU flag]] for AMD-V is "svm". This may be checked in [[Comparison of BSD operating systems|BSD derivatives]] via [[dmesg]] or [[sysctl]] and in [[Linux]] via <code>/proc/[[cpuinfo]]</code>.<ref name=cpuflag/> Instructions in AMD-V include VMRUN, VMLOAD, VMSAVE, CLGI, VMMCALL, INVLPGA, SKINIT, and STGI.

With some [[motherboard]]s, users must enable AMD SVM feature in the [[BIOS]] setup before applications can make use of it.<ref>{{Cite web |title=How to enable Intel VTx and AMD SVM? |website=Support |publisher=QNAP Systems, Inc. |url=https://www.qnap.com/en/how-to/faq/article/how-to-enable-intel-vtx-and-amd-svm|access-date=2020-12-23|archive-url=https://web.archive.org/web/20180307204640/https://www.qnap.com/en/how-to/faq/article/how-to-enable-intel-vtx-and-amd-svm |archive-date=2018-03-07 |url-status=dead}}</ref>

==== {{Anchor|Intel-VT-x|VMCS-SHADOWING}}Intel virtualization (VT-x) ====
{{Redirect|Intel VT-x|the Itanium virtualization extensions|Intel VT-i}}

<!--
  IOMMU stuff ("VT-d") belongs in [[IOMMU]] page or section
-->
[[File:Intel Core i7-940 bottom.jpg|thumb|right|[[List of Intel Core i7 microprocessors#"Bloomfield" (45 nm)|Intel Core i7]] (Bloomfield) CPU]]

Previously codenamed "Vanderpool", VT-x represents Intel's technology for virtualization on the x86 platform. On November 14, 2005, Intel released two models of [[Pentium 4]] (Model 662 and 672) as the first Intel processors to support VT-x. The CPU flag for VT-x capability is "vmx"; in Linux, this can be checked via <code>/proc/cpuinfo</code>, or in [[macOS]] via <code>sysctl machdep.cpu.features</code>.<ref name=cpuflag>[http://software.intel.com/en-us/blogs/2012/03/12/how-to-start-intel-hardware-assisted-virtualization-hypervisor-on-linux-to-speed-up-intel-android-x86-gingerbread-emulator To see if your processor supports hardware virtualization] {{webarchive |url=https://web.archive.org/web/20121125081532/http://software.intel.com/en-us/blogs/2012/03/12/how-to-start-intel-hardware-assisted-virtualization-hypervisor-on-linux-to-speed-up-intel-android-x86-gingerbread-emulator/ |date=2012-11-25}} Intel 2012.</ref><ref>https://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%20662%203.6%20GHz%20-%20HH80547PG1042MH.html</ref><ref>https://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%20672%203.8%20GHz%20-%20HH80547PG1122MH.html</ref>

"VMX" stands for Virtual Machine Extensions, which adds 13 new instructions: VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, VMXON, INVEPT, INVVPID, and VMFUNC.<ref>
{{cite web |url=http://software.intel.com/en-us/articles/intel-sdm |title=Intel® 64 and IA-32 Architectures Software Developer's Manual |last1=INTEL |date=October 2019 |website=intel.com |publisher=Intel Corporation |access-date=2020-01-04 }}</ref> These instructions permit entering and exiting a virtual execution mode where the guest OS perceives itself as running with full privilege (ring 0), but the host OS remains protected.

{{As of|2015}}, almost all newer server, desktop and mobile Intel processors support VT-x, with some of the [[Intel Atom]] processors as the primary exception.<ref>{{cite web |url=http://ark.intel.com/VTList.aspx |title=Intel Virtualization Technology List |publisher=Ark.intel.com |access-date=2010-05-02 |url-status=live |archive-url=http://archive.wikiwix.com/cache/20101027065321/http://ark.intel.com/VTList.aspx |archive-date=2010-10-27}}</ref> With some [[motherboard]]s, users must enable Intel's VT-x feature in the [[BIOS]] setup before applications can make use of it.<ref>{{cite web |url=http://www.microsoft.com/windows/virtual-pc/support/configure-bios.aspx |title=Windows Virtual PC: Configure BIOS |publisher=Microsoft |access-date=2010-09-08 |url-status=dead |archive-url=https://web.archive.org/web/20100906162731/http://www.microsoft.com/windows/virtual-pc/support/configure-bios.aspx |archive-date=2010-09-06}}</ref>

Intel started to include [[Extended Page Table]]s (EPT),<ref>{{cite journal |last=Neiger |first=Gil |author2=A. Santoni |author3=F. Leung |author4=D. Rodgers |author5=R. Uhlig |title=Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization |journal=Intel Technology Journal |year=2006 |volume=10 |issue=3 |pages=167–178 |publisher=Intel |url=http://download.intel.com/technology/itj/2006/v10i3/v10-i3-art01.pdf |doi=10.1535/itj.1003.01 |access-date=2008-07-06 |url-status=dead |archive-url=https://web.archive.org/web/20120925205120/http://download.intel.com/technology/itj/2006/v10i3/v10-i3-art01.pdf |archive-date=2012-09-25}}</ref> a technology for page-table virtualization,<ref>{{cite web |last=Gillespie |first=Matt |title=Best Practices for Paravirtualization Enhancements from Intel Virtualization Technology: EPT and VT-d |work=Intel Software Network |publisher=Intel |date=2007-11-12 |url=http://software.intel.com/en-us/articles/best-practices-for-paravirtualization-enhancements-from-intel-virtualization-technology-ept-and-vt-d |access-date=2008-07-06 |url-status=live |archive-url=https://web.archive.org/web/20081226043414/http://software.intel.com/en-us/articles/best-practices-for-paravirtualization-enhancements-from-intel-virtualization-technology-ept-and-vt-d |archive-date=2008-12-26}}</ref> since the [[Nehalem (microarchitecture)|Nehalem]] architecture,<ref>{{cite press release |title=First the Tick, Now the Tock: Next Generation Intel Microarchitecture (Nehalem) |publisher=Intel |url=http://www.intel.com/pressroom/archive/reference/whitepaper_Nehalem.pdf |access-date=2008-07-06 |url-status=live |archive-url=https://web.archive.org/web/20090126145628/http://www.intel.com/pressroom/archive/reference/whitepaper_Nehalem.pdf |archive-date=2009-01-26}}</ref><ref>{{cite web |title=Technology Brief: Intel Microarchitecture Nehalem Virtualization Technology |publisher=Intel |date=2009-03-25 |url=http://download.intel.com/business/resources/briefs/xeon5500/xeon_5500_virtualization.pdf |access-date=2009-11-03 |url-status=live |archive-url=https://web.archive.org/web/20110607125400/http://download.intel.com/business/resources/briefs/xeon5500/xeon_5500_virtualization.pdf |archive-date=2011-06-07}}</ref> released in 2008. In 2010, [[Westmere (microarchitecture)|Westmere]] added support for launching the logical processor directly in [[real mode]]{{snd}} a feature called "unrestricted guest", which requires EPT to work.<ref>[http://2013.asiabsdcon.org/papers/abc2013-P5A-paper.pdf] "Intel added unrestricted guest mode on Westmere micro-architecture and later Intel CPUs, it uses EPT to translate guest physical address access to host physical address. With this mode, VMEnter without enable paging is allowed."</ref><ref>[https://web.archive.org/web/20130418014840/http://download.intel.com/products/processor/manual/326019.pdf] "If the “unrestricted guest” VM-execution control is 1, the “enable EPT” VM-execution control must also be 1"</ref>

Since the [[Haswell (microarchitecture)|Haswell]] microarchitecture (announced in 2013), Intel started to include ''VMCS shadowing'' as a technology that accelerates [[Virtualization#Nested virtualization|nested virtualization]] of VMMs.<ref>{{cite web | url = http://www-ssl.intel.com/content/dam/www/public/us/en/documents/white-papers/intel-vmcs-shadowing-paper.pdf | title = 4th-Gen Intel Core vPro Processors with Intel VMCS Shadowing | year = 2013 | access-date = 2014-12-16 | publisher = [[Intel]] }}</ref>
The ''virtual machine control structure'' (VMCS) is a [[data structure]] in memory that exists exactly once per VM, while it is managed by the VMM. With every change of the execution context between different VMs, the VMCS is restored for the current VM, defining the state of the VM's virtual processor.<ref>[http://download.microsoft.com/download/9/8/f/98f3fe47-dfc3-4e74-92a3-088782200fe7/TWAR05015_WinHEC05.ppt Understanding Intel Virtualization Technology (VT).] {{webarchive |url=https://web.archive.org/web/20140908110038/http://download.microsoft.com/download/9/8/f/98f3fe47-dfc3-4e74-92a3-088782200fe7/TWAR05015_WinHEC05.ppt |date=September 8, 2014}} Retrieved 2014-09-01</ref> As soon as more than one VMM or nested VMMs are used, a problem appears in a way similar to what required shadow page table management to be invented, as described [[#SWBASED|above]]. In such cases, VMCS needs to be shadowed multiple times (in case of nesting) and partially implemented in software in case there is no hardware support by the processor. To make shadow VMCS handling more efficient, Intel implemented hardware support for VMCS shadowing.<ref>[http://searchservervirtualization.techtarget.com/feature/The-what-where-and-why-of-VMCS-shadowing The 'what, where and why' of VMCS shadowing.] {{webarchive |url=https://web.archive.org/web/20140903165257/http://searchservervirtualization.techtarget.com/feature/The-what-where-and-why-of-VMCS-shadowing |date=2014-09-03}} Retrieved 2014-09-01</ref>

==== VIA virtualization (VIA VT) ====
[[VIA Nano]] 3000 Series Processors and higher support VIA VT virtualization technology compatible with Intel VT-x.<ref>[http://www.via.com.tw/en/resources/pressroom/pressrelease.jsp?press_release_no=4247 VIA Introduces New VIA Nano 3000 Series Processors] {{webarchive |url=https://web.archive.org/web/20130122011049/http://www.via.com.tw/en/resources/pressroom/pressrelease.jsp?press_release_no=4247 |date=January 22, 2013}}</ref> EPT is present in [[Zhaoxin]] ZX-C, a descendant of [[List of VIA Nano microprocessors#QuadCore-E|VIA QuadCore-E]] & [[List of VIA Eden microprocessors#Eden C|Eden X4]] similar to Nano [[List of VIA Nano microprocessors#Nano C|C4350AL]].<ref>{{cite web |url=http://en.zhaoxin.com/Upload/201707061728050030.pdf |title=Notebook Solution: Kaixian ZX-C Processor + VX11PH Chipset}}</ref>

==== {{Anchor|INTERRUPT}}Interrupt virtualization (AMD AVIC and Intel APICv) ====
In 2012, AMD announced their ''Advanced Virtual Interrupt Controller'' (''AVIC'') targeting interrupt overhead reduction in virtualization environments.<ref>Wei Huang, [http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller Introduction of AMD Advanced Virtual Interrupt Controller] {{webarchive |url=https://web.archive.org/web/20140714160016/http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller |date=2014-07-14}}, XenSummit 2012</ref> This technology, as announced, does not support [[Advanced Programmable Interrupt Controller|x2APIC]].<ref>{{cite web
 |url         = http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf
 |title       = Next-generation Interrupt Virtualization for KVM
 |date        = August 2012
 |access-date  = 2014-07-12
 |author      = Jörg Rödel
 |publisher   = AMD
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20160304203744/http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf
 |archive-date = 2016-03-04
}}</ref>
In 2016, AVIC is available on the AMD family 15h models 6Xh
(Carrizo) processors and newer.<ref>{{cite web |url=http://www.mail-archive.com/xen-devel@lists.xen.org/msg81719.html |title=[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC |website=www.mail-archive.com |access-date=4 May 2018 |url-status=live |archive-url=https://web.archive.org/web/20170202040420/https://www.mail-archive.com/xen-devel@lists.xen.org/msg81719.html |archive-date=2 February 2017}}</ref>

Also in 2012, Intel announced a similar technology for interrupt and [[Advanced Programmable Interrupt Controller|APIC]] virtualization, which did not have a brand name at its announcement time.<ref>{{cite web
 |url         = http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf
 |title       = Reviewing Unused and New Features for Interrupt/APIC Virtualization
 |date        = 2012-12-13
 |access-date  = 2014-07-12
 |author      = Jun Nakajimaa
 |publisher   = Intel
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20150421073147/http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf
 |archive-date = 2015-04-21
}}</ref>
Later, it was branded as ''APIC virtualization'' (''APICv'')<ref>{{cite web
 |url         = http://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone
 |title       = APIC Virtualization Performance Testing and Iozone
 |date        = 2013-12-17
 |access-date  = 2014-07-12
 |author      = Khang Nguyen
 |website     = software.intel.com
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20140714142551/https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone
 |archive-date = 2014-07-14
}}</ref>
and it became commercially available in the [[Ivy Bridge (microarchitecture)|Ivy Bridge EP]] series of Intel CPUs, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).<ref>{{cite web
 |url         = http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf
 |title       = Product Brief Intel Xeon Processor E5-4600 v2 Product Family
 |date        = 2014-03-14
 |access-date  = 2014-07-12
 |publisher   = Intel
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20140714145052/http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf
 |archive-date = 2014-07-14
}}</ref>