Editing XAUI (section)

==Applications==
===Intended Use===
The implementation of XAUI as an optional XGMII Extender is primarily intended as a chip-to-chip ([[integrated circuit]] to integrated circuit) interface implemented with traces on a [[printed circuit board]]. Where the XGMII is electrically limited to distances of approximately 7&nbsp;cm, the XGMII Extender allows distances up to approximately 50&nbsp;cm.

===Rate of operation===
The XGMII Extender supports the 10&nbsp;Gbit/s [[bit rate|data rate]] of the XGMII. The 10&nbsp;Gbit/s MAC data stream is converted into four lanes at the XGMII (by the Reconciliation Sublayer for transmit or the PHY for receive). The byte stream of each lane is 8b/10b encoded by the XGXS for transmission across the XAUI at a nominal rate of 3.125 [[Baud|gigabaud]]. The XGXS at the PHY end of the XGMII Extender (PHY XGXS) and the XGXS at the RS end (DTE XGXS) may operate on independent clocks.

===Allocation of functions===
The XGMII Extender is transparent to the Reconciliation Sublayer and PHY device and operates symmetrically with similar functions on the [[Data terminal equipment|DTE]] transmit and receive data paths. The XGMII Extender is logically composed of two XGXSs interconnected with a XAUI data path in each direction. One XGXS acts as the source to the XAUI data path in the DTE transmit path and as the destination in the receive path. The other XGXS is the destination in the transmit path and source in the receive path. Each XAUI data path is composed of four serial lanes. All specifications for the XGMII Extender are written assuming conversion from XGMII to XAUI and back to XGMII, but other techniques may be employed provided that the result is that the XGMII Extender operates as if all specified conversions had been made. One example of this is the use of the optional XAUI with the 10GBASE-LX4 8b/10b PHY, where the XGXS interfacing to the Reconciliation Sublayer provides the PCS and PMA functionality required by the PHY. An XGXS layer is not required at the PHY end of the XAUI in this case. However, means may still be required to remove jitter introduced on the XAUI in order to meet PHY jitter requirements.