Editing Addressing mode (section)

==={{anchor|multilevel memory indirect}}Multi-level memory indirect===
If the word size is larger than the address, then the word referenced for memory-indirect addressing could itself have an indirect flag set to indicate another memory indirect cycle. This flag is referred to as an '''indirection bit''', and the resulting pointer is a [[tagged pointer]], the indirection bit tagging whether it is a direct pointer or an indirect pointer. Care is needed to ensure that a chain of indirect addresses does not refer to itself; if it does, one can get an [[infinite loop]] while trying to resolve an address.

The [[IBM 1620]], the [[Data General Nova]], and the [[HP 2100]] series each have such a multi-level memory indirect, and could enter such an infinite address calculation loop. The memory indirect addressing mode on the Nova influenced the invention of [[threaded code#Development|indirect threaded code]].

The DEC [[PDP-10]] computer with [[18-bit computing|18-bit]] addresses and [[36-bit computing|36-bit]] words allowed multi-level indirect addressing with the possibility of using an index register at each stage as well.  The priority interrupt system was queried before decoding of every address word.<ref>{{cite book |title=DEC-10-HMAA-D: PDP-10 KA10 Central Processor Maintenance Manual |date=December 1968 |publisher=[[Digital Equipment Corporation]] |location=[[Maynard, Massachusetts]] |pages=2–11 |edition=1st Printing |url=http://bitsavers.org/pdf/dec/pdp10/KA10/DEC-10-HMAA_D_KA10_Maint_Dec68.pdf#page=23 |access-date=15 May 2021 |format=PDF |quote=Figure 2-9: Effective Address Calculation: test "PI RQ ?"}}</ref>  So, an indirect address loop would not prevent execution of device service routines, including any [[Preemption (computing)#Preemptive multitasking|preemptive multitasking]] scheduler's time-slice expiration handler.  A looping instruction would be treated like any other compute-bound job.