Editing CPU cache (section)

===={{Anchor|UOP-CACHE}}Micro-operation (μop or uop) cache====
A '''micro-operation cache''' ('''μop cache''', '''uop cache''' or '''UC''')<ref>{{cite web |author=Kanter |first=David |date=September 25, 2010 |title=Intel's Sandy Bridge Microarchitecture – Instruction Decode and uop Cache |url=http://www.realworldtech.com/sandy-bridge/4/ |website=Real World Technologies}}</ref> is a specialized cache that stores [[micro-operation]]s of decoded instructions, as received directly from the [[instruction decoder]]s or from the instruction cache. When an instruction needs to be decoded, the μop cache is checked for its decoded form which is re-used if cached; if it is not available, the instruction is decoded and then cached.

One of the early works describing μop cache as an alternative frontend for the Intel [[P6 (microarchitecture)|P6 processor family]] is the 2001 paper ''"Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA"''.<ref name="uop-intel">{{cite conference |conference=2001 International Symposium on Low Power Electronics and Design (ISLPED'01), August 6-7, 2001 |location=Huntington Beach, CA, USA |last1=Solomon |first1=Baruch |book-title=ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design |last2=Mendelson |first2=Avi |last3=Orenstein |first3=Doron |last4=Almog |first4=Yoav |last5=Ronen |first5=Ronny |date=August 2001 |publisher=[[Association for Computing Machinery]] |isbn=978-1-58113-371-4 |pages=4–9 |title=Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA |doi=10.1109/LPE.2001.945363 |access-date=2013-10-06 |url=http://cecs.uci.edu/~papers/compendium94-03/papers/2001/islped01/pdffiles/p004.pdf |s2cid=195859085}}</ref> Later, Intel included μop caches in its [[Sandy Bridge]] processors and in successive microarchitectures like [[Ivy Bridge (microarchitecture)|Ivy Bridge]] and [[Haswell (microarchitecture)|Haswell]].<ref name="agner.org">{{cite web |author=Fog |first=Agner |author-link=Agner Fog |date=2014-02-19 |title=The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers |url=http://www.agner.org/optimize/microarchitecture.pdf |access-date=2014-03-21 |website=agner.org}}</ref>{{rp|121&ndash;123}}<ref name="anandtech-haswell">{{cite web |author=Shimpi |first=Anand Lal |date=2012-10-05 |title=Intel's Haswell Architecture Analyzed |url=http://www.anandtech.com/show/6355/intels-haswell-architecture/6 |access-date=2013-10-20 |publisher=[[AnandTech]]}}</ref> AMD implemented a μop cache in their [[Zen (microarchitecture)|Zen microarchitecture]].<ref>{{cite web |author=Cutress |first=Ian |date=2016-08-18 |title=AMD Zen Microarchitecture: Dual Schedulers, Micro-Op Cache and Memory Hierarchy Revealed |url=http://www.anandtech.com/show/10578/amd-zen-microarchitecture-dual-schedulers-micro-op-cache-memory-hierarchy-revealed |access-date=2017-04-03 |publisher=AnandTech}}</ref>

Fetching complete pre-decoded instructions eliminates the need to repeatedly decode variable length complex instructions into simpler fixed-length micro-operations, and simplifies the process of predicting, fetching, rotating and aligning fetched instructions. A μop cache effectively offloads the fetch and decode hardware, thus decreasing [[power consumption]] and improving the frontend supply of decoded micro-operations. The μop cache also increases performance by more consistently delivering decoded micro-operations to the backend and eliminating various bottlenecks in the CPU's fetch and decode logic.<ref name="uop-intel" /><ref name="anandtech-haswell" />

A μop cache has many similarities with a trace cache, although a μop cache is much simpler thus providing better power efficiency; this makes it better suited for implementations on battery-powered devices. The main disadvantage of the trace cache, leading to its power inefficiency, is the hardware complexity required for its [[heuristic]] deciding on caching and reusing dynamically created instruction traces.<ref name="tc-slides">{{cite web |last1=Gu |first1=Leon |last2=Motiani |first2=Dipti |date=October 2003 |title=Trace Cache |url=https://www.cs.cmu.edu/afs/cs/academic/class/15740-f03/www/lectures/TraceCache_slides.pdf |access-date=2013-10-06}}</ref>