Editing CPU cache (section)

====Branch target instruction cache====
A '''branch target cache''' or '''branch target instruction cache''', the name used on [[ARM microprocessors]],<ref>{{cite web |author=Niu |first=Kun |date=28 May 2015 |title=How does the BTIC (branch target instruction cache) work? |url=https://community.arm.com/processors/f/discussions/5320/how-does-the-btic-branch-target-instruction-cache-works |access-date=7 April 2018}}</ref> is a specialized cache which holds the first few instructions at the destination of a taken branch. This is used by low-powered processors which do not need a normal instruction cache because the memory system is capable of delivering instructions fast enough to satisfy the CPU without one. However, this only applies to consecutive instructions in sequence; it still takes several cycles of latency to restart instruction fetch at a new address, causing a few cycles of pipeline bubble after a control transfer. A branch target cache provides instructions for those few cycles avoiding a delay after most taken branches.

This allows full-speed operation with a much smaller cache than a traditional full-time instruction cache.