Editing ARM architecture family (section)

===Thumb-2===
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''Thumb-2'' technology was introduced in the ''ARM1156&nbsp;core'', announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory.

Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional execution. At the same time, the ARM instruction set was extended to maintain equivalent functionality in both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition, or on its inverse. When compiling into ARM code, this is ignored, but when compiling into Thumb it generates an actual instruction. For example:

<syntaxhighlight lang="nasm">
; if (r0 == r1)
CMP r0, r1
ITE EQ        ; ARM: no code ... Thumb: IT instruction
; then r0 = r2;
MOVEQ r0, r2  ; ARM: conditional; Thumb: condition via ITE 'T' (then)
; else r0 = r3;
MOVNE r0, r3  ; ARM: conditional; Thumb: condition via ITE 'E' (else)
; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE".
</syntaxhighlight>

All ARMv7 chips support the Thumb instruction set. All chips in the Cortex-A series that support ARMv7, all Cortex-R series, and all ARM11 series support both "ARM instruction set state" and "Thumb instruction set state", while chips in the [[ARM Cortex-M|Cortex-M]] series support only the Thumb instruction set.<ref>{{cite web |url=https://www.arm.com/products/CPUs/architecture.html |title=ARM Processor Instruction Set Architecture |publisher=ARM.com |access-date=18 April 2009 |archive-url=https://web.archive.org/web/20090415171228/http://arm.com/products/CPUs/architecture.html |archive-date=15 April 2009 |url-status=live}}</ref><ref>{{cite web |url=http://www.linuxdevices.com/news/NS7814673959.html |title=ARM aims son of Thumb at uCs, ASSPs, SoCs |publisher=Linuxdevices.com |access-date=18 April 2009 |archive-url=https://archive.today/20121209133741/http://www.linuxfordevices.com/c/a/News/ARM-aims-son-of-Thumb-at-uCs-ASSPs-SoCs/ |archive-date=9 December 2012 |url-status=dead}}</ref><ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/I1005458.html |title=ARM Information Center |publisher=Infocenter.arm.com |access-date=18 April 2009}}</ref>