Editing Peripheral Component Interconnect (section)

====Target burst termination====
The target requests the initiator end a burst by asserting STOP#.  The initiator will then end the transaction by deasserting FRAME# at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction.  There are several ways for the target to do this:

; Disconnect with data
: If the target asserts STOP# and TRDY# at the same time, this indicates that the target wishes this to be the last data phase.  For example, a target that does not support burst transfers will always do this to force single-word PCI transactions.  This is the most efficient way for a target to end a burst.
; Disconnect without data
: If the target asserts STOP# without asserting TRDY#, this indicates that the target wishes to stop without transferring data.  STOP# is considered equivalent to TRDY# for the purpose of ending a data phase, but no data is transferred.
; Retry
: A Disconnect without data before transferring any data is a ''retry'', and unlike other PCI transactions, PCI initiators are required to pause slightly before continuing the operation.  See the PCI specification for details.
; Target abort
: Normally, a target holds DEVSEL# asserted through the last data phase.  However, if a target deasserts DEVSEL# before disconnecting without data (asserting STOP#), this indicates a ''target abort'', which is a fatal error condition.  The initiator may not retry, and typically treats it as a [[bus error]].  A target may not deassert DEVSEL# while waiting with TRDY# or STOP# low; it must do this at the beginning of a data phase.

It will always take at least one cycle for the initiator to notice a target-initiated disconnection request and respond by deasserting FRAME#.  There are two sub-cases, which take the same amount of time, but one requires an additional data phase:

; Disconnect-A
: If the initiator observes STOP# before asserting its own IRDY#, then it can end the burst by deasserting FRAME# at the same time as it asserts IRDY#, ending the burst after the current data phase.
; Disconnect-B
: If the initiator has already asserted IRDY# (without deasserting FRAME#) by the time it observes the target's STOP#, it is committed to an additional data phase.  The target must wait through an additional data phase without data, holding STOP# asserted without TRDY#, before the transaction can end.

If the initiator ends the burst at the same time as the target requests disconnection, there is no additional bus cycle.