Editing ARM architecture family (section)

==={{anchor|VFP}}Floating-point (VFP)===
''VFP'' (Vector Floating Point) technology is a [[floating-point unit]] (FPU) coprocessor extension to the ARM architecture<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473e/CHDHAGGE.html |title=ARM Compiler toolchain Using the Assembler – VFP coprocessor |publisher=ARM.com |access-date=20 August 2014}}</ref> (implemented differently in Armv8 – coprocessors not defined there). It provides low-cost [[single-precision floating-point format|single-precision]] and [[double-precision floating-point format|double-precision floating-point]] computation fully compliant with the ''[[IEEE 754|ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic]]''. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true [[single instruction, multiple data]] (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction,<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdehgeh.html |title=VFP directives and vector notation |publisher=ARM.com |access-date=21 November 2011}}</ref> to be replaced with the much more powerful Advanced SIMD, also named [[#Advanced SIMD (Neon)|Neon]].

Some devices such as the ARM Cortex-A8 have a cut-down ''VFPLite'' module instead of a full VFP module, and require roughly ten times more clock cycles per float operation.<ref name="cortex_a9">{{cite web |url=https://www.shervinemami.info/armAssembly.html#cortex-a9 |title=Differences between ARM Cortex-A8 and Cortex-A9 |publisher=Shervin Emami |access-date=21 November 2011}}</ref> Pre-Armv8 architecture implemented floating-point/SIMD with the coprocessor interface. Other floating-point and/or SIMD units found in ARM-based processors using the coprocessor interface include [[Floating Point Accelerator|FPA]], FPE, [[MMX (instruction set)|iwMMXt]], some of which were implemented in software by trapping but could have been implemented in hardware. They provide some of the same functionality as VFP but are not [[opcode]]-compatible with it. FPA10 also provides [[extended precision]], but implements correct rounding (required by IEEE&nbsp;754) only in single precision.<ref>{{cite web |url=http://chrisacorns.computinghistory.org.uk/docs/GECPlessey/GECPlessey_FPA10DataSheet.pdf |title=FPA10 Data Sheet |author=<!--Not stated--> |date=11 June 1993 |website=chrisacorns.computinghistory.org.uk |publisher=GEC Plessey Semiconductors |access-date=26 November 2020 |quote=In relation to IEEE 754-1985, the FPA achieves conformance in single-precision arithmetic [...] Occasionally, double- and extended-precision multiplications may be produced with an error of 1 or 2 units in the least significant place of the mantissa.}}</ref>

; VFPv1: Obsolete
; VFPv2: An optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures. VFPv2 has 16 64-bit FPU registers.
; VFPv3 or VFPv3-D32: Implemented on most Cortex-A8 and A9 ARMv7 processors.  It is backward-compatible with VFPv2, except that it cannot trap floating-point exceptions. VFPv3 has 32 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such that constants can be loaded into FPU registers.
; VFPv3-D16: As above, but with only 16 64-bit FPU registers. Implemented on Cortex-R4 and R5 processors and the [[Tegra|Tegra 2]] (Cortex-A9).
; VFPv3-F16: Uncommon; it supports [[half-precision floating-point format|IEEE754-2008 half-precision (16-bit) floating point]] as a storage format.
; VFPv4 or VFPv4-D32:Implemented on Cortex-A12 and A15 ARMv7 processors, Cortex-A7 optionally has VFPv4-D32 in the case of an FPU with Neon.<ref name="VFPv4.A7">{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464f/BABDAHCE.html |title=Cortex-A7 MPCore Technical Reference Manual – 1.3 Features |publisher=ARM |access-date=11 July 2014}}</ref> VFPv4 has 32 64-bit FPU registers as standard, adds both half-precision support as a storage format and [[fused multiply–add|fused multiply-accumulate]] instructions to the features of VFPv3.
; VFPv4-D16: As above, but it has only 16 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors in the case of an FPU without Neon.<ref name="VFPv4.A7"/>
; VFPv5-D16-M: Implemented on Cortex-M7 when single and double-precision floating-point core option exists.

In [[Debian]] [[Linux]] and derivatives such as [[Ubuntu]] and [[Linux Mint]], '''armhf''' ('''ARM hard float''') refers to the ARMv7 architecture including the additional VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.<ref>{{cite web |url=https://wiki.debian.org/ArmHardFloatPort |title=ArmHardFloatPort – Debian Wiki |publisher=Wiki.debian.org |date=20 August 2012 |access-date=8 January 2014}}</ref>