Editing Dynamic random-access memory (section)

====Extended data out DRAM====
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[[Image:Pair32mbEDO-DRAMdimms.jpg|thumb|A pair of 32&nbsp;[[Megabyte|MB]] EDO DRAM modules]]

Extended data out DRAM (EDO DRAM) was invented and patented in the 1990s by [[Micron Technology]] who then licensed technology to many other memory manufacturers.<ref>{{cite book | author=S. Mueller | title=Upgrading and Repairing Laptops | year=2004 | publisher=Que; Har/Cdr Edition | page=221 | isbn=9780789728005 |url=https://books.google.com/books?id=xCXVGneKwScC}}</ref> EDO RAM, sometimes referred to as ''hyper page mode'' enabled DRAM, is similar to fast page mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance.<ref name=IBM96b>{{cite tech report |type=Applications Note |title=EDO (Hyper Page Mode)|url=https://www.ardent-tool.com/memory/pdf/edo.pdf |publisher=[[IBM]]|date=6 June 1996|archive-url=https://web.archive.org/web/20211202232211/https://ardent-tool.com/memory/pdf/edo.pdf|archive-date=2021-12-02|quote=a new address can be provided for the next access cycle before completing the current cycle allowing a shorter {{overline|CAS}} pulse width, dramatically decreasing cycle times.}}</ref> It is up to 30% faster than FPM DRAM,<ref>{{cite web|last1=Lin|first1=Albert|title=Memory Grades, the Most Confusing Subject|url=https://simmtester.com/News/PublicationArticle/11|website=Simmtester.com|publisher=CST, Inc.|access-date=1 November 2017|date=20 December 1999|url-status=live|archive-url=https://web.archive.org/web/20200812212321/https://simmtester.com/News/PublicationArticle/11|archive-date=2020-08-12|quote=So for the same –60 part, EDO DRAM is about 30% faster than FPM DRAM in peak data rate.}}</ref> which it began to replace in 1995 when [[Intel]] introduced the [[Mercury chipset|430FX chipset]] with EDO DRAM support. Irrespective of the performance gains, FPM and EDO SIMMs can be used interchangeably in many (but not all) applications.<ref>{{cite web|last1=Huang|first1=Andrew|title=Bunnie's RAM FAQ|url=http://www.bunniestudios.com/bunnie/dramfaq/DRAMFAQ.html|date=14 September 1996|url-status=live|archive-url=https://web.archive.org/web/20170612210850/http://www.bunniestudios.com/bunnie/dramfaq/DRAMFAQ.html|archive-date=12 June 2017}}</ref><ref>{{cite journal|author1=Cuppu, Vinodh|author2=Jacob, Bruce|author3=Davis, Brian|author4=Mudge, Trevor|title=High-Performance DRAMs in Workstation Environments|journal=IEEE Transactions on Computers|date=November 2001|volume=50|issue=11|pages=1133–1153|url=http://www.bunniestudios.com/bunnie/dramfaq/dram-workstation.pdf|access-date=2 November 2017|doi=10.1109/12.966491|hdl=1903/7456|url-status=live|archive-url=https://web.archive.org/web/20170808082644/http://www.bunniestudios.com/bunnie/dramfaq/dram-workstation.pdf|archive-date=8 August 2017|hdl-access=free}}</ref>

To be precise, EDO DRAM begins data output on the falling edge of {{overline|CAS}} but does not disable the output when {{overline|CAS}} rises again. Instead, it holds the current output valid (thus extending the data output time) even as the DRAM begins decoding a new column address, until either a new column's data is selected by another {{overline|CAS}} falling edge, or the output is switched off by the rising edge of {{overline|RAS}}.  (Or, less commonly, a change in {{overline|CS}}, {{overline|OE}}, or {{overline|WE}}.)

This ability to start a new access even before the system has received the preceding column's data made it possible to design memory controllers which could carry out a {{overline|CAS}} access (in the currently open row) in one clock cycle, or at least within two clock cycles instead of the previously required three. EDO's capabilities were able to partially compensate for the performance lost due to the lack of an L2 cache in low-cost, commodity PCs. More expensive notebooks also often lacked an L2 cache die to size and power limitations, and benefitted similarly. Even for systems ''with'' an L2 cache, the availability of EDO memory improved the average memory latency seen by applications over earlier FPM implementations.

Single-cycle EDO DRAM became very popular on video cards toward the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM.