Editing CPU cache (section)

===={{Anchor|INCLUSIVE|EXCLUSIVE}}Exclusive versus inclusive====
Multi-level caches introduce new design decisions. For instance, in some processors, all data in the L1 cache must also be somewhere in the L2 cache. These caches are called ''strictly inclusive''. Other processors (like the [[AMD Athlon]]) have ''exclusive'' caches: data are guaranteed to be in at most one of the L1 and L2 caches, never in both. Still other processors (like the Intel [[Pentium II]], [[Pentium III|III]], and [[Pentium 4|4]]) do not require that data in the L1 cache also reside in the L2 cache, although it may often do so. There is no universally accepted name for this intermediate policy;<ref>{{cite web
 | url = http://www.amecomputers.com/explanation-of-the-l1-and-l2-cache.html
 | title = Explanation of the L1 and L2 Cache
 | access-date = 2014-06-09
 | website = amecomputers.com
 | archive-date = 2014-07-14
 | archive-url = https://web.archive.org/web/20140714181050/http://www.amecomputers.com/explanation-of-the-l1-and-l2-cache.html
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 }}</ref><ref name="ispass04">{{cite conference |last1=Zheng |first1=Ying |last2=Davis |first2=Brian T. |last3=Jordan |first3=Matthew |date=10–12 March 2004 |title=Performance Evaluation of Exclusive Cache Hierarchies |url=http://mercury.pr.erau.edu/~davisb22/papers/ispass04.pdf |conference=IEEE International Symposium on Performance Analysis of Systems and Software |location=Austin, Texas, USA |pages=89–96 |doi=10.1109/ISPASS.2004.1291359 |isbn=0-7803-8385-0 |archive-url=https://web.archive.org/web/20120813003941/http://mercury.pr.erau.edu/~davisb22/papers/ispass04.pdf |archive-date=2012-08-13 |access-date=2014-06-09 |url-status=dead}}</ref> two common names are "non-exclusive" and "partially-inclusive".

The advantage of exclusive caches is that they store more data. This advantage is larger when the exclusive L1 cache is comparable to the L2 cache, and diminishes if the L2 cache is many times larger than the L1 cache. When the L1 misses and the L2 hits on an access, the hitting cache line in the L2 is exchanged with a line in the L1. This exchange is quite a bit more work than just copying a line from L2 to L1, which is what an inclusive cache does.<ref name="ispass04" />

One advantage of strictly inclusive caches is that when external devices or other processors in a multiprocessor system wish to remove a cache line from the processor, they need only have the processor check the L2 cache. In cache hierarchies which do not enforce inclusion, the L1 cache must be checked as well. As a drawback, there is a correlation between the associativities of L1 and L2 caches: if the L2 cache does not have at least as many ways as all L1 caches together, the effective associativity of the L1 caches is restricted. Another disadvantage of inclusive cache is that whenever there is an eviction in L2 cache, the (possibly) corresponding lines in L1 also have to get evicted in order to maintain inclusiveness. This is quite a bit of work, and would result in a higher L1 miss rate.<ref name="ispass04" />

Another advantage of inclusive caches is that the larger cache can use larger cache lines, which reduces the size of the secondary cache tags. (Exclusive caches require both caches to have the same size cache lines, so that cache lines can be swapped on a L1 miss, L2 hit.) If the secondary cache is an order of magnitude larger than the primary, and the cache data are an order of magnitude larger than the cache tags, this tag area saved can be comparable to the incremental area needed to store the L1 cache data in the L2.<ref>{{cite web |author1=Jaleel |first=Aamer |author2=Eric Borch |last3=Bhandaru |first3=Malini |last4=Steely Jr. |first4=Simon C. |last5=Emer |first5=Joel |date=2010-09-27 |title=Achieving Non-Inclusive Cache Performance with Inclusive Caches |url=http://www.jaleels.org/ajaleel/publications/micro2010-tla.pdf |access-date=2014-06-09 |website=jaleels.org}}</ref>