Editing Dynamic random-access memory (section)

==={{Anchor|ROW-ACTIVATION}}Synchronous dynamic RAM===
{{Main|Synchronous dynamic random-access memory}}
Synchronous dynamic RAM (SDRAM) significantly revises the asynchronous memory interface, adding a clock (and a clock enable) line.  All other signals are received on the rising edge of the clock.

The {{overline|RAS}} and {{overline|CAS}} inputs no longer act as strobes, but are instead, along with {{overline|WE}}, part of a 3-bit command:
{| class="wikitable"
|+ SDRAM Command summary
! {{overline|CS}}
! {{overline|RAS}}
! {{overline|CAS}}
! {{overline|WE}}
! Address
! Command
|-
| {{no|H}} || {{n/a|x}} || {{n/a|x}} || {{n/a|x}} || {{n/a|x}} || Command inhibit (no operation)
|-
| {{yes|L}} || {{no|H}} || {{no|H}} || {{no|H}} || {{n/a|x}} || No operation
|-
| {{yes|L}} || {{no|H}} || {{no|H}} || {{yes|L}} || {{n/a|x}} || Burst Terminate: stop a read or write burst in progress.
|-
| {{yes|L}} || {{no|H}} || {{yes|L}} || {{no|H}} || style="text-align:center;" | Column || Read from currently active row.
|-
| {{yes|L}} || {{no|H}} || {{yes|L}} || {{yes|L}} || style="text-align:center;" | Column || Write to currently active row.
|-
| {{yes|L}} || {{yes|L}} || {{no|H}} || {{no|H}} || style="text-align:center;" | Row || Activate a row for read and write.
|-
| {{yes|L}} || {{yes|L}} || {{no|H}} || {{yes|L}} || {{n/a|x}} || Precharge (deactivate) the current row.
|-
| {{yes|L}} || {{yes|L}} || {{yes|L}} || {{no|H}} || {{n/a|x}} || Auto refresh: refresh one row of each bank, using an internal counter.
|-
| {{yes|L}} || {{yes|L}} || {{yes|L}} || {{yes|L}} || style="text-align:center;" | Mode || Load mode register: address bus specifies DRAM operation mode.
|}

The {{overline|OE}} line's function is extended to a per-byte DQM signal, which controls data input (writes) in addition to data output (reads).  This allows DRAM chips to be wider than 8 bits while still supporting byte-granularity writes.

Many timing parameters remain under the control of the DRAM controller. For example, a minimum time must elapse between a row being activated and a read or write command. One important parameter must be programmed into the SDRAM chip itself, namely the [[CAS latency]].  This is the number of clock cycles allowed for internal operations between a read command and the first data word appearing on the data bus.  The ''Load mode register'' command is used to transfer this value to the SDRAM chip.  Other configurable parameters include the length of read and write bursts, i.e. the number of words transferred per read or write command.

The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip.  Using a few bits of ''bank address'' that accompany each command, a second bank can be activated and begin reading data ''while a read from the first bank is in progress''.  By alternating banks, a single SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot.

====Single data rate synchronous DRAM====
{{See also|Synchronous dynamic random-access memory|l1=SDR SDRAM}}

Single data rate SDRAM (SDR SDRAM or SDR) is the original generation of SDRAM; it made a single transfer of data per clock cycle.

====Double data rate synchronous DRAM====
{{Main|DDR SDRAM|DDR2 SDRAM|DDR3 SDRAM|DDR4 SDRAM|DDR5 SDRAM}}
[[File:SAMSUNG@DDR-SDRAM@64MBit@K4D62323HA-QC60 Stack-DSC03539-DSC03556 - ZS-DMap.jpg|thumb|The [[die (integrated circuit)|die]] of a Samsung DDR-SDRAM 64-MBit package]]
Double data rate SDRAM (DDR SDRAM or DDR) was a later development of SDRAM, used in PC memory beginning in 2000. Subsequent versions are numbered sequentially (''DDR2'', ''DDR3'', etc.).  DDR SDRAM internally performs double-width accesses at the clock rate, and uses a [[double data rate]] interface to transfer one half on each clock edge.  DDR2 and DDR3 increased this factor to 4× and 8×, respectively, delivering 4-word and 8-word bursts over 2 and 4 clock cycles, respectively.  The internal access rate is mostly unchanged (200 million per second for DDR-400, DDR2-800 and DDR3-1600 memory), but each access transfers more data.

====Direct Rambus DRAM====
{{Main|RDRAM}}

''Direct RAMBUS DRAM'' (''DRDRAM'') was developed by Rambus. First supported on [[motherboard]]s in 1999, it was intended to become an industry standard, but was outcompeted by [[DDR SDRAM]], making it technically obsolete by 2003.

====Reduced Latency DRAM====
{{Main|RLDRAM}}

Reduced Latency DRAM (RLDRAM) is a high performance double data rate (DDR) SDRAM that combines fast, random access with high bandwidth, mainly intended for networking and caching applications.