Editing PCI Express (section)

=== Physical layer <span class="anchor" id="PHYSICAL-LAYER"></span> ===
{| class="wikitable floatright" style="margin-left: 1.5em; margin-right: 0; margin-top: 0;"
|+ Connector pins and lengths
|-
! rowspan="2" | Lanes
! colspan="2" | Pins
! colspan="2" | Length
|-
! Total
! Variable
! Total
! Variable
|-
| {{0}}x1 || 2×18 = {{0}}36<ref name="9tQ3g" /> || 2×{{0}}7 = {{0}}14 || 25&nbsp;mm || {{0}}7.65&nbsp;mm
|-
| {{0}}x4 || 2×32 = {{0}}64 || 2×21 = {{0}}42 || 39&nbsp;mm || 21.65&nbsp;mm
|-
| {{0}}x8 || 2×49 = {{0}}98 || 2×38 = {{0}}76 || 56&nbsp;mm || 38.65&nbsp;mm
|-
| {{0}}x16 || 2×82 = 164 || 2×71 = 142 || 89&nbsp;mm || 71.65&nbsp;mm
|}

[[File:PCIe J1900 SoC ITX Mainboard IMG 1820.JPG|thumb|An open-end PCI Express x1 connector lets longer cards that use more lanes be plugged while operating at x1 speeds.]]

The PCIe Physical Layer (''PHY'', ''PCIEPHY'', ''PCI Express PHY'', or ''PCIe PHY'') specification is divided into two sub-layers, corresponding to electrical and logical specifications. The logical sublayer is sometimes further divided into a MAC sublayer and a PCS, although this division is not formally part of the PCIe specification. A specification published by Intel, the PHY Interface for PCI Express (PIPE),<ref name="pipe_spec" /> defines the MAC/PCS functional partitioning and the interface between these two sub-layers. The PIPE specification also identifies the ''physical media attachment'' (PMA) layer, which includes the [[SerDes|serializer/deserializer (SerDes)]] and other analog circuitry; however, since SerDes implementations vary greatly among [[Application-specific integrated circuit|ASIC]] vendors, PIPE does not specify an interface between the PCS and PMA.

At the electrical level, each lane consists of two unidirectional [[Differential signaling|differential pair]]s operating at 2.5, 5, 8, 16 or 32&nbsp;[[Gigabit|Gbit]]/s, depending on the negotiated capabilities. Transmit and receive are separate differential pairs, for a total of four data wires per lane.

A connection between any two PCIe devices is known as a ''link'', and is built up from a collection of one or more ''lanes''. All devices must minimally support single-lane (x1) link. Devices may optionally support wider links composed of up to 32 lanes.<ref name="PCIe-System-Architecture">{{Cite web|url=https://www.mindshare.com/files/ebooks/PCI%20Express%20System%20Architecture.pdf|title=PCI Express System Architecture}}</ref><ref name="Intel-PCIe">{{Cite web|url=https://www.intel.com/content/www/us/en/support/ru-banner.html|title=Communications|website=Intel}}</ref> This allows for very good compatibility in two ways:
* A PCIe card physically fits (and works correctly) in any slot that is at least as large as it is (e.g., a x1 sized card works in any sized slot);
* A slot of a large physical size (e.g., x16) can be wired electrically with fewer lanes (e.g., x1, x4, x8, or x12) as long as it provides the ground connections required by the larger physical slot size.
In both cases, PCIe negotiates the highest mutually supported number of lanes. Many graphics cards, motherboards and [[BIOS]] versions are verified to support x1, x4, x8 and x16 connectivity on the same connection.

The width of a PCIe connector is 8.8&nbsp;mm, while the height is 11.25&nbsp;mm, and the length is variable. The fixed section of the connector is 11.65&nbsp;mm in length and contains two rows of 11 pins each (22 pins total), while the length of the other section is variable depending on the number of lanes. The pins are spaced at 1&nbsp;mm intervals, and the thickness of the card going into the connector is 1.6&nbsp;mm.<ref name="pcie_schematics1" /><ref name="pcie_schematics2" />

==== Data transmission ====
PCIe sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency is still comparable to conventional PCI, which has dedicated interrupt lines. When the problem of IRQ sharing of pin based interrupts is taken into account and the fact that message signaled interrupts (MSI) can bypass an I/O APIC and be delivered to the CPU directly, MSI performance ends up being substantially better.<ref name="vV4Hv" />

Data transmitted on multiple-lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCIe specification refers to this interleaving as ''data striping''. While requiring significant hardware complexity to synchronize (or [[clock skew|deskew]]) the incoming striped data, striping can significantly reduce the latency of the ''n''th byte on a link. While the lanes are not tightly synchronized, there is a limit to the ''lane to lane skew'' of 20/8/6&nbsp;ns for 2.5/5/8&nbsp;GT/s so the hardware buffers can re-align the striped data.<ref name="iPAaS" /> Due to padding requirements, striping may not necessarily reduce the latency of small data packets on a link.

As with other high data rate serial transmission protocols, the clock is [[self-clocking signal|embedded]] in the signal. At the physical level, PCI Express 2.0 utilizes the [[8b/10b encoding]] scheme<ref name="faq3" /> (line code) to ensure that strings of consecutive identical digits (zeros or ones) are limited in length. This coding was used to prevent the receiver from losing track of where the bit edges are. In this coding scheme every eight (uncoded) payload bits of data are replaced with 10 (encoded) bits of transmit data, causing a 20% overhead in the electrical bandwidth. To improve the available bandwidth, PCI Express version 3.0 instead uses [[64b/66b encoding|128b/130b]] encoding (1.54% overhead). [[Line encoding]] limits the run length of identical-digit strings in data streams and ensures the receiver stays synchronised to the transmitter via [[clock recovery]].

A desirable balance (and therefore [[spectral density]]) of 0 and 1 bits in the data stream is achieved by [[XOR]]ing a known [[Linear-feedback shift register|binary polynomial]] as a "[[scrambler]]" to the data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by applying the XOR a second time. Both the scrambling and descrambling steps are carried out in hardware.

Dual simplex in PCIe means there are two simplex channels on every PCIe lane. Simplex means communication is only possible in one direction. By having two simplex channels, two-way communication is made possible. One differential pair is used for each channel.<ref>{{cite web |title=PCIe Data Transmission Overview  |website=[[Microchip Technology]] |url=https://ww1.microchip.com/downloads/aemDocuments/documents/TCG/ProductDocuments/Brochures/00003818.pdf }}</ref><ref name="auto"/><ref>{{cite book | url=https://books.google.com/books?id=k_HJCgAAQBAJ&dq=pcie+differential+pair&pg=PT128 | isbn=978-0-7686-9003-3 | title=CompTIA A+ Exam Cram (Exams 220-602, 220-603, 220-604) | date=19 July 2007 | publisher=Pearson Education }}</ref>