Editing CPU cache (section)

===More hierarchies===
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Other processors have other kinds of predictors (e.g., the store-to-load bypass predictor in the [[Digital Equipment Corporation|DEC]] [[Alpha 21264]]), and various specialized predictors are likely to flourish in future processors.

These predictors are caches in that they store information that is costly to compute. Some of the terminology used when discussing predictors is the same as that for caches (one speaks of a '''hit''' in a branch predictor), but predictors are not generally thought of as part of the cache hierarchy.

The K8 keeps the instruction and data caches '''[[cache coherency|coherent]]''' in hardware, which means that a store into an instruction closely following the store instruction will change that following instruction. Other processors, like those in the Alpha and MIPS family, have relied on software to keep the instruction cache coherent. Stores are not guaranteed to show up in the instruction stream until a program calls an operating system facility to ensure coherency.