Editing Serial Peripheral Interface (section)

===Intel's Enhanced Serial Peripheral Interface===
[[Intel]] has developed a successor to its [[Low Pin Count]] (LPC) bus that it calls the '''Enhanced Serial Peripheral Interface (eSPI)''' bus. Intel aims to reduce the number of pins required on motherboards and increase throughput compared to LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous [[Out-of-band signal|out-of-band]] pins through eSPI, and allow system designers to trade off cost and performance.<ref name="eSPI">{{cite report |title=Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms) |date=January 2016 |version=Revision 1.0 |url=https://www-ssl.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf |publisher=Intel |access-date=2017-02-05 |id=Document number 327432-004}}</ref><ref>{{cite report |id=Document Number 327432-001EN |title=Enhanced Serial Peripheral Interface (eSPI) Interface Specification (for Client Platforms) |date=May 2012 |version=Revision 0.6 |url=https://downloadmirror.intel.com/21353/eng/eSPI%20Specification%20rev0.6%20(client).pdf |publisher=Intel |access-date=2017-02-05}}</ref>

An eSPI bus can either be shared with SPI devices to save pins or be separate from an SPI bus to allow more performance, especially when eSPI devices need to use SPI flash devices.<ref name="eSPI" />

This standard defines an Alert# signal that is used by an eSPI slave to request service from the master. In a performance-oriented design or a design with only one eSPI slave, each eSPI slave will have its Alert# pin connected to an Alert# pin on the eSPI master that is dedicated to each slave, allowing the eSPI master to grant low-latency service, because the eSPI master will know which eSPI slave needs service and will not need to poll all of the slaves to determine which device needs service. In a budget design with more than one eSPI slave, all of the Alert# pins of the slaves are connected to one Alert# pin on the eSPI master in a [[wired-OR]] connection, which requires the master to poll all the slaves to determine which ones need service when the Alert# signal is pulled low by one or more peripherals that need service. Only after all of the devices are serviced will the Alert# signal be pulled high due to none of the eSPI slaves needing service and therefore pulling the Alert# signal low.<ref name="eSPI" />

This standard allows designers to use 1-bit, 2-bit, or 4-bit communications at speeds from 20 to 66&nbsp;MHz to further allow designers to trade off performance and cost.<ref name="eSPI" />

Communications that were out-of-band of LPC like [[general-purpose input/output]] (GPIO) and [[System Management Bus]] (SMBus) should be tunneled through eSPI via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins from motherboard designs using eSPI.<ref name="eSPI" />

This standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data, short memory cycles with lengths of 1, 2, or 4 bytes that have much less overhead compared to standard memory cycles, and I/O cycles with lengths of 1, 2, or 4 bytes of data which are low overhead as well. This significantly reduces overhead compared to the LPC bus, where all cycles except for the 128-byte firmware hub read cycle spends more than one-half of all of the bus's throughput and time in overhead. The standard memory cycle allows a length of anywhere from 1 byte to 4 kilobytes in order to allow its larger overhead to be amortised over a large transaction. eSPI slaves are allowed to initiate bus master versions of all of the memory cycles. Bus master I/O cycles, which were introduced by the LPC bus specification, and ISA-style DMA including the 32-bit variant introduced by the LPC bus specification, are not present in eSPI. Therefore, bus master memory cycles are the only allowed DMA in this standard.<ref name="eSPI" />

eSPI slaves are allowed to use the eSPI master as a proxy to perform flash operations on a standard SPI flash memory slave on behalf of the requesting eSPI slave.<ref name="eSPI" />

64-bit memory addressing is also added, but is only permitted when there is no equivalent 32-bit address.<ref name="eSPI" />

The Intel [[Z170|Z170 chipset]] can be configured to implement either this bus or a variant of the LPC bus that is missing its ISA-style DMA capability and is underclocked to 24&nbsp;MHz instead of the standard 33&nbsp;MHz.<ref>{{Cite web | url = https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/100-series-chipset-datasheet-vol-1.pdf | title = Intel® 100 Series Chipset Family PCH Datasheet, Vol. 1 | access-date = April 15, 2015}}</ref>

The eSPI bus is also adopted by [[AMD Ryzen]] chipsets.