Editing AMD K5 (section)

== Models ==
{{Main|List of AMD K5 processors}}
There were two revisions of the K5 architecture, internally called the '''SSA/5''' and the '''5k86''', both released with the K5 label. The original set of "SSA/5" CPUs had its branch prediction unit disabled and additional internal waitstates added; these issues were remedied with the "5k86", resulting in up to 30% better performance clock for clock.<ref>{{cite web |url=http://alasir.com/x86ref/index2.html |title=X86 CPU Reference (Part 2) |website=alasir.com |access-date=12 January 2022 |archive-url=https://web.archive.org/web/20170726175647/http://alasir.com/x86ref/index2.html |archive-date=26 July 2017 |url-status=dead}}</ref><ref>{{cite web | url=https://wccftech.com/microprocessor-history-amd-k5/ | title=Microprocessor History - AMD K5 | date=May 2019 }}</ref> The "SSA/5" line ran from 75 to 100&nbsp;MHz; the "5k86" line ran from 90 to 133&nbsp;MHz. However, AMD used what it called a [[PR rating]], or performance rating, to label the chips according to their suggested equivalence in integer performance to a Pentium of that clock speed. Thus, a 116&nbsp;MHz chip from the second line was marketed as the "K5 PR166". Manufacturing delays caused the PR200's arrival to nearly align with the release of K6. Since AMD did not want the two chips competing, the K5-PR200 only arrived in small numbers.

===SSA/5===
[[Image:AMD5k86-P90 SSA5-90ABQ.jpg|thumb|AMD 5K86-P90 (SSA/5)]]
[[Image:AMD_K5_PR75_die.JPG|thumb|AMD K5 PR75 (SSA/5) die shot]]
* Sold as '''5K86''' P75 to P100, later as '''K5''' PR75 to PR100
* 4.3 million transistors in 500 or 350&nbsp;nm
* L1-Cache: 8 + 16 KB (data + instructions)
* [[Socket 5]] and [[Socket 7]]
* VCore: 3.52&nbsp;V
* [[Front side bus]]: 50 (PR75), 60 (PR90), 66&nbsp;MHz (PR100)
* First release: March 27, 1996
* Clockrate: 75, 90, 100&nbsp;MHz

===5k86===
[[File:AMD K5 die2.JPG|thumb|AMD K5 PR150 (5k86) die shot]]
* Sold as '''K5''' PR120 to PR166; later PR200
* 4.3 million transistors in 350&nbsp;nm
* L1-Cache: 8 + 16 KB (data + instructions)
* [[Socket 5]] and [[Socket 7]]
* VCore: 3.52&nbsp;V
* [[Front side bus]]: 60 (PR120/150), 66&nbsp;MHz
* First release: October 7, 1996
* Clockrate: 90 (PR120), 100 (PR133), 105 (PR150), 116.6 (PR166), 133&nbsp;MHz (PR200)