Editing ANTIC (section)

== Registers ==
The Atari 8-bit computers and the Atari 5200 console map the ANTIC chip to the $D4xx<sub>hex</sub> page.

ANTIC provides 15 Read/Write registers controlling Playfield display parameters, DMA for Player/Missile graphics, fine scrolling, light pen input, and interrupts.  Hardware registers do not return the written values back when read.  This problem is solved by Operating System Shadow registers implemented in regular RAM as places to store the last value written to registers.   Operating System Shadow registers are copied from RAM to the hardware registers during the vertical blank.   Therefore, any writes to hardware registers which have corresponding shadow registers will be overwritten by the value of the Shadow registers during the next vertical blank.

Some Write hardware registers do not have corresponding Shadow registers.  They can be safely written by an application without the value being overwritten during the vertical blank. If the application needs to know the last state of the register then it is the responsibility of the application to remember what it wrote.

Operating System Shadow registers also exist for some Read registers where reading the value directly from hardware at an unknown stage in the display cycle may return inconsistent results.

{| class="wikitable sortable"
|-
! Name !! class="unsortable"|Description !! Read/Write !! class="unsortable"|Hex Addr !! Dec Addr !! Shadow Name !! class="unsortable"|Shadow Hex Addr !! Shadow Dec Addr 
|-
| [[ANTIC#DMACTL $D400 Write|DMACTL]] || Direct Memory Access Control || Write || $D400 || 54272 || SDMCTL || $022F || 559
|-
| [[ANTIC#CHACTL $D401 Write|CHACTL]] || Character Control || Write || $D401 || 54273 || CHART || $02F3 || 755
|-
| [[ANTIC#DLISTL/DLISTH $D402/$D403 Write|DLISTL]] || Display List Pointer (low byte) || Write || $D402 || 54274 || SDLSTL || $0230 || 560
|-
| [[ANTIC#DLISTL/DLISTH $D402/$D403 Write|DLISTH]] || Display List Pointer (high byte) || Write || $D403 || 54275 || SDLSTH || $0231 || 561
|-
| [[ANTIC#HSCROL $D404 Write|HSCROL]] || Horizontal Fine Scroll || Write || $D404 || 54276 || || || 
|-
| [[ANTIC#VSCROL $D405 Write|VSCROL]] || Vertical Fine Scroll || Write || $D405 || 54277 || || || 
|-
| [[ANTIC#PMBASE $D407 Write|PMBASE]] || Player/Missile Base Address || Write || $D407 || 54279 || || || 
|-
| [[ANTIC#CHBASE $D409 Write|CHBASE]] || Character Set Base Address || Write || $D409 || 54281 || CHBAS || $02F4 || 756
|-
| [[ANTIC#WSYNC $D40A Write|WSYNC]] || Wait for Horizontal Sync || Write || $D40A || 54282 || || || 
|-
| [[ANTIC#VCOUNT $D40B Read|VCOUNT]] || Vertical Line Counter || Read || $D40B || 54283 || || || 
|-
| [[ANTIC#PENH $D40C Read|PENH]] || Light Pen Horizontal Position || Read || $D40C || 54284 || LPENH || $0234 || 564
|-
| [[ANTIC#PENV $D40D Read|PENV]] || Light Pen Vertical Position || Read || $D40D || 54285 || LPENV || $0235 || 565
|-
| [[ANTIC#NMIEN $D40E Write|NMIEN]] || Non-Maskable Interrupt (NMI) Enable || Write || $D40E || 54286 || || || 
|-
| [[ANTIC#NMIRES $D40F Write|NMIRES]] || Non-Maskable Interrupt (NMI) Reset || Write || $D40F || 54287 || || || 
|-
| [[ANTIC#NMIST $D40F Read|NMIST]] || Non-Maskable Interrupt (NMI) Status || Read || $D40F || 54287 || || || 
|}

In the individual register listings below the following legend applies:
{| class="wikitable sortable"
|-
! Bit Value !! Description 
|-
|  0  || Bit must be 0
|-
|  1  || Bit must be 1
|-
|  ?  || Bit may be either 0 or 1, and is used for a purpose.
|-
|  -  || Bit is unused, or should not be expected to be a certain value
|-
| label || Refer to a later explanation for the purpose of the bit.
|}

=== DMACTL $D400 Write ===
SHADOW: SDMCTL $022F

Direct Memory Access (DMA) Control

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| - || - || Display List DMA || Player Missile Resolution || Player DMA || Missile DMA || Playfield Width || Playfield Width 
|}

DMACTL controls ANTIC's DMA behavior for the Playfield and Player-Missile ([[Sprite (computer graphics)|sprite]]) graphics.

'''Playfield Width''' bit values:
{| class="wikitable"
|-
! Playfield Width Bits [1:0] !! Description !! Size 
|-
| 0 0 = $00 || Disable playfield ||
|-
| 0 1 = $01 || Narrow playfield || 128 color clocks/256 high-res pixels
|-
| 1 0 = $02 || Normal playfield || 160 color clocks/320 high-res pixels
|-
| 1 1 = $03 || Wide playfield || 192 color clocks/384 high-res pixels
|}

Also see Display List DMA bit regarding Playfield display.

'''Player/Missile DMA''' bits values:
{| class="wikitable"
|-
! Player/Missile DMA Bits [3:2] !! Description 
|-
| 0 0 = $00 || Disable Player and Missile DMA
|-
| 0 1 = $04 || Enable Missile DMA
|-
| 1 0 = $08 || Enable Player DMA
|-
| 1 1 = $0C || Enable Player and Missile DMA
|}

ANTIC's Player/Missile DMA feature reads bytes from memory and delivering data to update [[CTIA and GTIA|CTIA/GTIA]]'s GRAFP0, GRAFP1, GRAFP2, GRAFP3, and GRAFM graphics pattern registers relieving the CPU from creating Player/Missile ([[Sprite (computer graphics)|sprite]]) graphics.  These bits turn on ANTIC's transmission of Player data and Missile data to CTIA/GTIA. CTIA/GTIA must also be configured to receive the data via its [[CTIA and GTIA#GRACTL $D01D Write|GRACTL]] register in order for Player/Missile DMA to function as expected.

When Player DMA is enabled, Missile DMA automatically occurs to keep the DMA timing consistent, but the data is not delivered to the Missile's GRAFM register.

When enabled, Player/Missile DMA occurs on every scan line in the visible display—from scan line 8 to 247.   Therefore, the Player/Missile data in the memory map (see ANTIC's [[ANTIC#PMBASE $D407 Write|PMBASE]]) above and below those scan line counts is unused and undisplayed.

'''Player/Missile Resolution''' bit values:
* $00 - Double line resolution.  ANTIC updates its DMA fetch address every other scan line and updates the [[CTIA and GTIA|CTIA/GTIA]] Player/Missile Graphics pattern registers every scan line, so that each Player/Missile byte pattern is two scan lines tall.  When Double line resolution is enabled [[CTIA and GTIA|CTIA/GTIA]] register [[CTIA and GTIA#VDELAY $D01C Write|VDELAY]] ($D01C<sub>hex</sub>/53276<sub>dec</sub>) works by masking updates on even scan lines which results in shifting the bit pattern of individual Players and Missiles down one scan line. 
* $10 - Single line resolution. A DMA fetch and Player/Missile register update occurs on every scan line.  [[CTIA and GTIA|CTIA/GTIA]] register [[CTIA and GTIA#VDELAY $D01C Write|VDELAY]] ($D01C<sub>hex</sub>/53276<sub>dec</sub>) which masks updates on even scan lines effectively reduces Single line resolution to Double line resolution.

ANTIC DMA and Player/Missile pattern register updates occur on each scan line regardless of resolution. When Double line resolution is in effect the Player/Missile memory can be modified between the redundant DMA fetches thus changing the pattern sent to the GRAF* registers and producing apparent Single line resolution Player/Missiles.

'''Display List DMA''' bit values:
* $00 - Disable Display List.
* $20 - Enable Display list.

Playfield display requires that Display List DMA is enabled, and a Playfield width specified. If either value is zero, then no Playfield display is generated.

=== CHACTL $D401 Write ===
SHADOW: CHART $02F3

Character Control

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| - || - || - || - || - || Video Reflect || Video Inverse || Video Blank 
|}

CHACTL controls character display.

Character control bit values do the following actions:

{| class="wikitable"
|-
! Feature !! Bits Value !! Description 
|-
| Video Blank || $01 || Inverse video characters display as blanks spaces.
|-
| Video Inverse || $02 || Inverse video characters appear as inverse video. (default)
|-
| Video Reflect || $04 || All characters are displayed vertically mirrored.
|}

The CHACTL Video Inverse and Video Blank bits affect the display of characters in ANTIC Text Modes 2 and 3 which have the high bit set (characters $80 through $FF).  Toggling the values of the CHACTL bits allow blinking or blanking these characters globally for the entire display.

Video Inverse and Video Blank enabled together result in reverse video characters displayed as an inverse blank space.  Video Inverse and Video Blank bits work in ANTIC modes 2 and 3, and have no effect on the other text modes 4, 5, 6, and 7.

The Video Reflect bit affects all Text Modes.  Video Reflect is useful for situations requiring mirroring effects without defining a new character set.  An ideal use is card games displaying accurate card faces showing upside down suits.    As this vertically mirrors the glyph data before it is used, the effect appears inconsistent for ANTIC Mode 3 descenders with glyph bytes 6 and 7 appearing at the bottom of the descender area.

=== DLISTL/DLISTH $D402/$D403 Write ===
SHADOW: SDLSTL/SDLSTH $0230/$0231

Display List Pointer

{| class="wikitable"
|-
! Bit 15 !! Bit 14 !! Bit 13 !! Bit 12 !! Bit 11 !! Bit 10 !! Bit 9 !! Bit 8 !! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} 
|}

ANTIC begins executing the [[Display list|Display List]] pointed to by the 16-bit address in registers DLISTL/DLISTH (D402-D403<sub>hex</sub>/54274-54275<sub>dec</sub>). The address registers are updated during Display List execution by ANTIC's JMP (Jump) and JVB (Jump and wait for Vertical Blank).  The address is also updated by the Operating System's Vertical Blank Interrupt (VBI) routine using the values in shadow registers SDLSTL/SDLSTH (0230-0231<sub>hex</sub>/560-561<sub>dec</sub>).

When the OS Vertical Blank Interrupt is enabled, direct updates to the ANTIC DLIST registers by the CPU or the ANTIC Jump instructions will be overwritten by the OS during the next Vertical Blank by the values in the shadow registers.  Therefore, page flipping implemented by [[Display list|Display List]]s that point to the next [[Display list|Display List]] in series will not operate as expected unless the Vertical Blank interrupt is disabled.

=== HSCROL $D404 Write ===
Horizontal Fine Scroll

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| {{sdash}} || {{sdash}} || {{sdash}} || {{sdash}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} 
|}

This register specifies the distance of the Horizontal fine scrolling shift in color clocks.  Only the lowest 4 bits are significant.  The value range of 16 color clocks allows ANTIC to shift Mode 2 Text four characters, and Mode 6 text two characters before a coarse scroll is needed.

When Horizontal scrolling is enabled for a mode line ANTIC fetches the next size increment greater than the current screen width to provide the buffer of data subject to the horizontal scrolling control. When displaying Narrow width ANTIC fetches the screen RAM needed for Normal width.  Likewise, for Normal width ANTIC fetches the screen RAM needed for Wide.

ANTIC buffers the first few bytes read from screen memory that are sufficient to cover the 16 color clock range of movement. (Two to four bytes depending on display mode.) The HSCROL value specifies how many color clocks should be output from the buffered data beginning from the last (right most) color clock of the last buffered byte and progressing to the left.  When HSCROL is 0 no color clocks are output from the buffer, so the first screen byte displayed is the first byte after the buffered data.  As HSCROL increases more color clocks from the end (right side) of the buffered data are added to the left edge of the display causing the fine scroll shift to move the screen contents to the right.

ANTIC Mode F (high-resolution, 1/2 color clock pixels) can only be scrolled two pixels at a time, because HSCROL specifies color clocks.

ANTIC Modes using the alternate [[CTIA and GTIA|GTIA]] color interpretations must be scrolled by an entire [[CTIA and GTIA|GTIA]] pixel (two color clocks).  Only even values should be used to ensure correct scrolling.  Odd values of HSCROL will shift the pixel stream into a different state that [[CTIA and GTIA|GTIA]] will interpret as different colors.

Unlike many platforms Atari's horizontal scrolling is visually consistent and free from color "strobing" artifacts due to Atari's pixel size matching the color clock timing needed for accurate color.

=== VSCROL $D405 Write ===
Vertical Fine Scroll

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| {{sdash}} || {{sdash}} || {{sdash}} || {{sdash}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} 
|}

This register specifies the distance of the Vertical fine scrolling in scan lines.  The lowest 4 bits are significant, however the Vertical scroll value should range from 0 to the ANTIC Mode line's scan line height&nbsp;-&nbsp;1.  Scrolling farther than the ANTIC Mode's number of scan lines results in lines of repeated data upsetting the fine scrolling continuity (though, this can also be used as an exploitable behavior).

The Vertical scrolling region is defined by setting the VS bit ($20) on a sequential series of ANTIC Mode Lines in the [[Display list|Display List]].  The first Mode line without the VS bit set becomes the end of the scrolling region and is used as a buffer line to supply the new information to scroll up into the bottom of the scrolling region.

The Vertical scroll value indicates the scan line number to begin the display in the first Mode line and is also used as the scan line number to end the display in the last Mode line (the line without the VS bit set).

Example: Given an eight scan line ANTIC Mode (Text Modes 2, 4, or 6) with the VS bit set on two adjacent Mode lines the scrolling region then consists of three Mode lines—the third line in the scrolling region is the first Mode line encountered without the VS bit set.  When Vertical scrolling is not set in the [[Display list|Display List]] the three Modes lines would naturally result in 24 displayed scan lines.  When the VS bits are set in the [[Display list|Display List]] Mode instructions as described and the VSCROL value is set to 2 then the first Mode line in the region begins displaying at scan line 2 showing scan lines 2 to 7 (six scan lines or 8&nbsp;-&nbsp;VSCROL), the second Mode line is displayed completely (eight scan lines), and the final Mode line ends at scan line 2 showing scan lines 0 to 2 (three scan lines or VSCROL&nbsp;+&nbsp;1).  The total scan lines displayed in the scrolling region is then 6&nbsp;+&nbsp;8&nbsp;+&nbsp;3&nbsp;=&nbsp;17 scan lines.

Since fine scrolling is based on scan lines not pixel height, and scrolling region movement is done simply by skipping scan lines from the first Mode line and adding scan lines to the last Mode line, it is possible to use different graphics Modes within the scrolling region.  This merely requires additional care when determining how many scan lines can be shifted for the current first and last Mode lines in the scrolling region.

Blank Mode lines cannot be contained within a scrolling region, because Blank Mode line instructions inherently do not have a Vertical Scroll Modifier bit.   (Blank Mode line instructions specify the blank line count using the bits 7 through 5 that function as LMS, HS, and VS Modifiers for "regular" Playfield Mode instructions.)  However, a Blank Mode instruction can be used to end a scrolling region and is still subject to the expected scan line height changes per the vertical scroll value.

=== PMBASE $D407 Write ===
Player Missile Base Address

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| ? || ? || ? || ? || ? || ? || ? || ? 
|}

This specifies the page of the base address for Player/Missile graphics.  When double line resolution P/M graphics are operating the PMBASE value must begin on a 1K boundary.  When single line resolution P/M graphics are operating the PMBASE value must begin on a 2K boundary.

=== CHBASE $D409 Write ===
SHADOW: CHBAS $02F4

Character Base Address

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| ? || ? || ? || ? || ? || ? || ? || ? 
|}

This specifies the page of the base address for the character set.  ANTIC Modes 2, 3, 4, and 5 use 128 characters in the character set and require the CHBASE value begin on a 1K boundary.  ANTIC Modes 6 and 7 use 64 characters, so the CHBASE value must begin on a 512 byte boundary.

The usual default value is $E0<sub>hex</sub>/224<sub>dec</sub> for the character set in ROM at $E000<sub>hex</sub>/57344<sub>dec</sub>.

=== WSYNC $D40A Write ===
Wait For Horizontal Sync

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| ? || ? || ? || ? || ? || ? || ? || ? 
|}

This register allows programs to synchronize to the display.  A write to this register halts the 6502 program through the end of the current scanline.  This behavior is commonly used during Display List Interrupts to produce clean transitions/changes from one scanline to the next.  The value written is unimportant.

=== VCOUNT $D40B Read ===
Vertical Line Counter

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| ? || ? || ? || ? || ? || ? || ? || ? 
|}

This register tracks the scan line currently being generated. The value returned is the actual scan line divided by 2.  Blank lines generated at the start of the display are included. The value for NTSC will range from 0 to 130 for NTSC, and 0 to 155 for PAL.   This value is useful during Display List Interrupts to identify the vertical screen position.

=== PENH $D40C Read ===
SHADOW: LPENH $0234

Light Pen Horizontal Position

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| ? || ? || ? || ? || ? || ? || ? || ? 
|}

This contains the horizontal color clock position when the light pen/light gun trigger is pressed.  The shadow register is the recommended source for reading this information, since it will be updated during the vertical blank guaranteeing consistent and reliable results.  Programs should avoid reading the hardware register directly unless the program is certain the register is read at a time insuring the value is valid.  Light guns for the Atari function the same way as light pens with the addition of an optical magnifier allowing the screen to be read from a greater distance.  The light pen/light gun input device requires a conventional CRT using a scanning electron beam.  The light pen/light gun cannot work with modern LCD TVs and monitors.

=== PENV $D40D Read ===
SHADOW: LPENV $0235

Light Pen Vertical Position

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| ? || ? || ? || ? || ? || ? || ? || ? 
|}

This contains the VCOUNT value captured when the light pen/light gun trigger is pressed.  The shadow register is the recommended source for reading this information, since it will be updated during the vertical blank guaranteeing consistent and reliable results.  Programs should avoid reading the hardware register directly unless the program is certain the register is read at a time insuring the value is valid.  Light guns for the Atari function the same way as light pens with the addition of an optical magnifier allowing the screen to be read from a greater distance.  The light pen/light gun input device requires a conventional CRT using a scanning electron beam.  The light pen/light gun cannot work with modern LCD TVs and monitors.

=== NMIEN $D40E Write ===
Non-Maskable Interrupt (NMI) Enable

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| DLI || VBI || RESET || - || - || - || - || - 
|}

NMIEN enables Non-Maskable Interrupts.  The bit values:

{| class="wikitable"
|-
! Feature !! Bits Value !! Description 
|-
| Reset || $20 || Enable Reset key interrupt 
|-
| VBI || $40 || Enable Vertical Blank Interrupt
|-
| DLI || $80 || Enable Display List Interrupt
|}

The Operation System sets NMIEN to the default $40<sub>hex</sub>/64<sub>dec</sub> during the power up routines.  The NMI service routines first vector through $FFFA<sub>hex</sub>/65530<sub>dec</sub> which determines the cause and then transfers control to the interrupt service routine.

'''DLI:'''

If NMIEN's DLI bit is set when ANTIC encounters a [[Display list|Display List]] instruction with the DLI modifier bit set, then ANTIC triggers the DLI on the last scan line of that Display List instruction mode line.

The Operating System does not use DLIs, so the default address for the DLI vector (VDSLST, $0200<sub>hex</sub>/512<sub>dec</sub>) points to an RTI instruction in ROM.   The application using DLIs must alter VDSLST to point to the desired DLI routine before enabling the DLI.

The 6502 Accumulator, X and Y register contents are not preserved before entry to the DLI routine. It is the responsibility of the DLI routine to save the state of the registers that will be used during the DLI routine, and then the last action is to restore the original values of the registers before exiting with an RTI instruction. Routines typically push the register values to the 6502 stack.

If multiple DLIs are used the first interrupt updates VDSLST to point to the address of the next interrupt, and so on for subsequent interrupts.  The last Display List Interrupt routine on the screen points VDSLST back to the address of the first Display List Interrupt.  Alternatively, a Vertical Blank Interrupt routine can be used to reset the VDSLST address to guarantee the DLIs remain in sync with the screen.

'''VBI:'''

When NMIEN's VBI bit is set, ANTIC will signals a Vertical Blank Interrupt at the end of processing the JVB (Jump vertical blank) at the end of the [[Display list|Display List]].   The Operating System  uses the Vertical Blank to perform various housekeeping chores (among other things - updating timers, copying controller input values to their Shadow registers, and copying the contents of Shadow registers to the custom chips hardware registers.)

The OS jumps through VVBLKI ($0222<sub>hex</sub>/546<sub>dec</sub>) to begin the OS VBI Service Routine, and the OS VBI Routine exits with a jump through VVBLKD ($0224<sub>hex</sub>/548<sub>dec</sub>).  By default VVBLKI points to the OS jump vector SYSVBV ($E45F<sub>hex</sub>/58463<sub>dec</sub>) to begin the Vertical Blank Interrupt, and VVBLKD points to the OS jump vector XITVBV ($E462<sub>hex</sub>/58466<sub>dec</sub>).

User programs can insert execution of custom code either before (Immediate) or after (Deferred) the Operating System's Vertical Blank Interrupt routines.  Since the OS Vertical Blank interrupt could be called while a user program is updating the vectors, the Operating system provides a routine, SETVBV ($E45C<sub>hex</sub>/58460<sub>dec</sub>), that will safely update the VVBLKI or VVBLKD vectors to point to a new routine:

* To set a new jump target for VVBLKI (Immediate) set the Y register to the low byte of the target address, the X register to the high byte of the target address, and the Accumulator to 6, then JSR SETVBV.  The user code called through VVBLKI simply needs to exit by jumping to the OS Vertical Blank with a JMP SYSVBV ($E45F<sub>hex</sub>/58463<sub>dec</sub>).
* To set a new jump target for VVBLKD (Deferred) set the Y register to the low byte of the target address, the X register to the high byte of the target address, and the Accumulator to 7, then JSR SETVBV..  The user code called through VVBLKD must exit by jumping to the OS Vertical Blank exit routine with a JMP XITVBV ($E462<sub>hex</sub>/58466<sub>dec</sub>).

When the CRITIC flag ($42<sub>hex</sub>/66<sub>dec</sub>) is non-zero execution of the Deferred Vertical Blank interrupt is suppressed regardless of the addresses in the vectors.  The default value of CRITIC, 0, allows execution of both Immediate and Deferred Vertical Blank Interrupts.

=== NMIRES $D40F Write ===
Non-Maskable Interrupt (NMI) Reset

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| ? || ? || ? || ? || ? || ? || ? || ? 
|}

Any value written to NMIRES resets the bits in NMIST which indicate the reason for the most recent Non-Maskable Interrupt.  This is used by interrupt dispatch code in the Operating System and there would ordinarily not be a reason for a user program to write here.

=== NMIST $D40F Read ===
Non-Maskable Interrupt (NMI) Status

{| class="wikitable"
|-
! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| DLI || VBI || RESET || - || - || - || - || - 
|}

The Operating System's Non-Maskable Interrupt dispatch routine reads this register to determine the reason for the interrupt and so which service routine to execute.

The bit values:

* $20 - Reset key interrupt
* $40 - Vertical Blank Interrupt 
* $80 - Display List Interrupt