Editing AVR microcontrollers (section)

=== Device architecture ===
[[File:AVR_ATXMEGA_128A1.JPG|right|thumb|Atmel ATxmega128A1 in 100-pin [[TQFP]] package]]
[[File:ATMEL MEGA32U4 (Micro Controller).png|thumb|ATMEL MEGA32U4 die shot]]
The AVRs have 32 [[Byte|single-byte]] [[Processor register|registers]] and are classified as 8-bit RISC devices.

[[Flash memory|Flash]], [[EEPROM]], and [[Static random-access memory|SRAM]] are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data memory or memory-mapped devices. Almost all devices (except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips.

==== Program memory ====
Program instructions are stored in [[non-volatile]] [[flash memory]]. Although the [[Microcontroller unit|MCUs]] are 8-bit, each instruction takes one or two 16-bit words. The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64&nbsp;KB of flash, while the ATmega32x line has 32&nbsp;KB). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC AVR/FPGA chips.

==== Internal data memory ====
The data [[address space]] consists of the [[register file]], I/O registers, and [[Static random-access memory|SRAM]]. Some small models also map the program ROM into the data address space, but larger models do not.

==== Internal registers ====
In the tinyAVR and megaAVR variants of the [[Atmel AVR instruction set|AVR architecture]], the working registers are mapped in as the first 32 data memory addresses (0000<sub>16</sub>–001F<sub>16</sub>), followed by 64 I/O registers (0020<sub>16</sub>–005F<sub>16</sub>). In devices with many peripherals, these registers are followed by 160 “extended I/O” registers, only accessible as [[memory-mapped I/O]] (0060<sub>16</sub>–00FF<sub>16</sub>).

Actual SRAM starts after these register sections, at address 0060<sub>16</sub> or, in devices with "extended I/O", at 0100<sub>16</sub>.

Even though there are separate addressing schemes and optimized opcodes for accessing the register file and the first 64 I/O registers, all can also be addressed and manipulated as if they were in SRAM.

The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15 are omitted) which are not addressable as memory locations. I/O memory begins at address 0000<sub>16</sub>, followed by SRAM. In addition, these devices have slight deviations from the standard AVR instruction set. Most notably, the direct load/store instructions (LDS/STS) have been reduced from 2 words (32 bits) to 1 word (16 bits), limiting the total direct addressable memory (the sum of both I/O and SRAM) to 128 bytes. Conversely, the indirect load instruction's (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash and configuration bits; therefore, the Load Program Memory (LPM) instruction is unnecessary and omitted. (For detailed info, see [[Atmel AVR instruction set]].)

In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000<sub>16</sub>–0FFF<sub>16</sub>). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (1000<sub>16</sub>–1FFF<sub>16</sub>). The actual SRAM is located after these ranges, starting at 2000<sub>16</sub>.

==== General-purpose input/output (GPIO) ports ====
Each [[GPIO]] port on a tiny or mega AVR drives up to eight pins and is controlled by three 8-bit registers: DDR''x'', PORT''x'' and PIN''x'', where ''x'' is the port identifier.

* DDR''x'': Data Direction Register, configures the pins as either inputs or outputs.
* PORT''x'': Output port register. Sets the output value on pins configured as outputs. Enables or disables the [[pull-up resistor]] on pins configured as inputs.
* PIN''x'': Input register, used to read an input signal. On some devices, this register can be used for pin toggling: writing a logic one to a PIN''x'' bit toggles the corresponding bit in PORT''x'', irrespective of the setting of the DDR''x'' bit.<ref>[http://www.atmel.com/Images/Atmel-2586-AVR-8-bit-Microcontroller-ATtiny25-ATtiny45-ATtiny85_Datasheet.pdf atmel.com]</ref>

Newer ATtiny AVRs, like ATtiny817 and its siblings, have their port control registers somewhat differently defined.
xmegaAVR have additional registers for push/pull, totem-pole and pullup configurations.

==== EEPROM ====
Almost all AVR microcontrollers have internal [[EEPROM]] for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed.

In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions, which makes EEPROM access much slower than other internal RAM.

However, some devices in the SecureAVR (AT90SC) family<ref>[http://www.atmel.com/images/doc1010.pdf Atmel Smart Card ICs]</ref> use a special EEPROM mapping to the data or program memory, depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space.

Since the number of writes to EEPROM is limited{{snd}} Atmel specifies 100,000 write cycles in their datasheets{{snd}} a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if the contents need to be changed.