Editing Adder (electronics) (section)

===Full adder===
A '''full adder''' adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds three one-bit numbers, often written as <math>A</math>, <math>B</math>, and <math>C_{in}</math>; <math>A</math> and <math>B</math> are the operands, and <math>C_{in}</math> is a bit carried in from the previous less-significant stage.<ref name="Mano_1979"/> The circuit produces a two-bit output. Output carry and sum are typically represented by the signals <math>C_{out}</math> and <math>S</math>, where the sum equals <math>2C_{out} + S</math>. The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers.

A full adder can be implemented in many different ways such as with a custom [[transistor]]-level circuit or composed of other gates. The most common implementation is with:

:<math>S = A \oplus B \oplus C_{in}</math>
:<math>C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B))</math>

The above expressions for <math>S</math> and <math>C_{in}</math> can be derived from using a [[Karnaugh map]] to simplify the truth table.

In this implementation, the final [[OR gate]] before the carry-out output may be replaced by an [[XOR gate]] without altering the resulting logic. This is because when A and B are both 1, the term <math>(A \oplus B)</math> is always 0, and hence <math>(C_{in} \cdot (A \oplus B))</math> can only be 0. Thus, the inputs to the final OR gate can never be both 1's (this is the only combination for which the OR and XOR outputs differ).

Due to the [[functional completeness]] property of the NAND and NOR gates, a full adder can also be implemented using nine [[NAND gates]],<ref>{{Citation|title=Half Adder and Full Adder Circuits|author-first=Ravi|author-last=Teja|date=2021-04-15|access-date=2021-07-27|url=https://www.electronicshub.org/half-adder-and-full-adder-circuits/#Full_Adder_using_NAND_Gates}}</ref> or nine [[NOR gates]].

Using only two types of gates is convenient if the circuit is being implemented using simple [[integrated circuit]] chips which contain only one gate type per chip.

A full adder can also be constructed from two half adders by connecting <math>A</math> and <math>B</math> to the input of one half adder, then taking its sum-output <math>S</math> as one of the inputs to the second half adder and <math>C_{in}</math> as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate. The sum-output from the second half adder is the final sum output (<math>S</math>) of the full adder and the output from the OR gate is the final carry output (<math>C_{out}</math>). The critical path of a full adder runs through both XOR gates and ends at the sum bit <math>S</math>. Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to:

:<math>T_\text{FA} = 2 \cdot T_\text{XOR} = 2 D</math>

The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carry-block and therefore, if AND or OR gates take 1 delay to complete, has a delay of:

:<math>T_\text{c} = T_\text{XOR} + T_\text{AND} + T_\text{OR} = D + D + D = 3D</math>

The [[truth table]] for the full adder is:
:{| class="wikitable" style="text-align:center"
|- style="background:#def; text-align:center;"
!colspan="3"| Inputs || colspan="2"| Outputs
|- style="background:#def; text-align:center;"
| '''A''' || '''B''' || '''C'''<sub>in</sub> || '''C'''<sub>out</sub>  || '''S'''
|- 
| {{no2|0}} || {{no2|0}} || {{no2|0}}  || {{no2|0}} || {{no2|0}}
|- 
| {{no2|0}} || {{no2|0}} || {{yes2|1}}  || {{no2|0}} || {{yes2|1}}
|- 
| {{no2|0}} || {{yes2|1}} || {{no2|0}}  || {{no2|0}} || {{yes2|1}}
|- 
| {{no2|0}} || {{yes2|1}} || {{yes2|1}}  || {{yes2|1}} || {{no2|0}}
|- 
| {{yes2|1}} || {{no2|0}} || {{no2|0}}  || {{no2|0}} || {{yes2|1}}
|- 
| {{yes2|1}} || {{no2|0}} || {{yes2|1}}  || {{yes2|1}} || {{no2|0}}
|- 
| {{yes2|1}} || {{yes2|1}} || {{no2|0}}  || {{yes2|1}} || {{no2|0}}
|- 
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}  || {{yes2|1}} || {{yes2|1}}
|-
|}
Inverting all inputs of a full adder also inverts all of its outputs, which can be used in the design of fast ripple-carry adders, because there is no need to invert the carry.<ref name="Fischer"/>

Various full adder digital logic circuits:
<gallery widths="220px" heights="165px">
File:Fulladder.gif|Full adder in action.
File:Full-adder logic diagram.svg|[[Schematic]] of full adder implemented with two [[XOR gate]]s, two [[AND gate]]s, one [[OR gate]].
File:Full Adder using NAND gates.svg|Schematic of full adder implemented with nine [[NAND gate]]s.
File:Full Adder using NOR gates.svg|Schematic of full adder implemented with nine [[NOR gate]]s.
File:Inverting full adder CMOS 24T.svg|Full adder with inverted outputs with single-transistor carry propagation delay in [[CMOS]]<ref name="Fischer"/>
File:1-bit full-adder.svg|[[Electronic symbol|Schematic symbol]] for a 1-bit full adder with ''C''<sub>in</sub> and ''C''<sub>out</sub> drawn on sides of block to emphasize their use in a multi-bit adder
</gallery>