Editing Barrel processor (section)

===Disadvantages===

There are a few disadvantages to barrel processors.

* The state of each thread must be kept on-chip, typically in registers, to avoid costly off-chip context switches. This requires a large number of registers compared to typical processors.
* Either all threads must share the same [[CPU cache|cache]], which slows overall system performance, or there must be one unit of cache for each execution thread, which can significantly increase the [[transistor count]] and thus the cost of such a CPU. However, in [[Real-time computing#Criteria for real-time computing|hard real-time]] [[embedded system]]s where barrel processors are often found, memory access costs are typically calculated assuming worst-case cache behavior, so this is a minor concern.{{cn|reason="Minor concern" seems to be too all-encompassing unless this is genuinely the case for all barrel processors|date=January 2020}} Some barrel processors such as the [[XMOS]] XS1 do not have a cache at all.