Editing Berkeley RISC (section)

==Follow-ons==

Work on the original RISC designs ended with RISC II, but the concept lived on at Berkeley. The basic core was re-used in ''SOAR'' in 1984, basically a RISC converted to run [[Smalltalk]] (in the same way that it could be claimed RISC ran [[C (programming language)|C]]), and later in the similar ''VLSI-BAM'' that ran [[Prolog]] instead of Smalltalk. Another effort was ''SPUR'', which was a full set of chips needed to build a full 32-bit [[workstation]].

The RISC concept, as developed in the Berkeley RISC, [[Stanford MIPS]], and [[IBM 801]] projects, influenced several commercial ISAs in the mid 1980s. Acorn Computers, in collaboration with silicon partner [[VLSI Technology]],<ref>{{Cite journal |last=Furber |first=Steve |date=March 2017 |title=Microprocessors: the engines of the digital age |url=https://royalsocietypublishing.org/doi/10.1098/rspa.2016.0893 |journal=Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences |language=en |volume=473 |issue=2199 |pages=20160893 |doi=10.1098/rspa.2016.0893 |issn=1364-5021 |pmc=5378251 |pmid=28413353}}</ref> developed the [[ARM architecture family|ARM architecture]], shipping ARM Evaluation Systems with their second generation ARM chipsets from July 1986,<ref>{{Cite web |title=Chris's Acorns: Acorn OEM Products |url=http://chrisacorns.computinghistory.org.uk/docs/Acorn/OEM/OEM.html |access-date=2025-04-24 |website=chrisacorns.computinghistory.org.uk}}</ref> and a range of desktop computers, branded [[Acorn Archimedes]], advertised as capable of 4 MIPS, from June 6, 1987.<ref>{{Cite web |title=Acorn advert: Archimedes: 1987 Microcomputer of the year |url=https://nosher.net/archives/computers/acorn_archie_percw_jan88 |access-date=2025-04-24 |website=nosher.net |language=en-GB}}</ref> [[Hewlett Packard]] introduced its own [[PA-RISC]] ISA, also in 1986, in new models of its [[HP 3000]] and [[HP 9000]] series. [[Sun Microsystems]], in collaboration with silicon partner [[Fujitsu]], shipped their own [[SPARC]] ISA, from July 8, 1987, in their [[Sun-4|Sun 4/260]], a machine advertised as offering 10 MIPS. [[MIPS Computer Systems]], founded in 1984 to commercialize the work of the Stanford MIPS project, developed the [[MIPS architecture]] and MIPS processors starting with the [[R2000 microprocessor|R2000]]; [[Silicon Graphics]] (SGI) replaced the [[Motorola 68000 series]] processors in their workstations with MIPS processors, eventually purchasing MIPS, and [[Digital Equipment Corporation]] used MIPS processors in their [[DECstation#DECstation RISC workstations|DECstation]] workstations. [[IBM]] developed the [[IBM ROMP|ROMP]] RISC processor, used in the [[IBM RT PC]], and the [[IBM POWER architecture|POWER architecture]], used in the [[RS/6000]] series. By the late 1980s, most large chip vendors followed, working on efforts like the [[Motorola 88000]], [[Fairchild Clipper]], and [[AMD 29000]]. The performance and efficiency of the systems exceeded the previous generation of CISC CPUs.

In the early 1990s, [[Apple Inc.|Apple]], IBM, and Motorola formed the [[AIM alliance]], which developed the [[PowerPC]] architecture, based on IBM's POWER architecture, with PowerPC processors sold both by IBM and Motorola, and used by Apple to replace the [[Motorola 68000 series]] processors in their [[Macintosh]] computers. [[Digital Equipment Corporation]] (DEC) had several RISC projects in development since the early 1980s, eventually settling on the [[DEC PRISM]], but that project was canceled; in the early 1990s, a subsequent project produced the [[DEC Alpha]].

On February 13, 2015, IEEE installed a plaque at Oracle Corporation in Santa Clara.<ref>{{Cite web|url=https://blogs.oracle.com/oracle-systems/oracle-to-receive-ieee-milestone-award-for-sparc-risc-architecture|title=Oracle to Receive IEEE Milestone Award for SPARC RISC Architecture|last=Gee|first=Kelvin|website=blogs.oracle.com|access-date=2020-03-19}}</ref> It reads

* ''Sun Microsystems introduced the Scalable Processor Architecture (SPARC) RISC in July 1987. Building on UC Berkeley RISC and Sun compiler and operating system developments, SPARC architecture was highly adaptable to evolving semiconductor, software, and system technology and user needs. The architecture delivered the highest performance, scalable workstations and servers, for engineering, business, Internet, and cloud computing uses.''

Techniques developed for and alongside the idea of the reduced instruction set have also been adopted in successively more powerful implementations and extensions of the traditional "complex" [[x86 architecture]]. Much of a modern microprocessor's transistor count is devoted to large caches, many [[instruction pipeline|pipeline]] stages, [[superscalar]] instruction dispatch, [[branch predictor|branch prediction]] and other modern techniques which are applicable regardless of instruction architecture. The amount of silicon dedicated to instruction decoding on a modern x86 implementation is proportionately quite small, so the distinction between "complex" and RISC processor implementations has become blurred.