Editing Burroughs Large Systems (section)

====System design====
The B5000 was unusual at the time in that the architecture and [[instruction set]] were designed with the needs of software taken into consideration. This was a large departure from the computer system design of the time, where a processor and its instruction set would be designed and then handed over to the software people.

The B5000, B5500 and B5700 in Word Mode has two different addressing modes, depending on whether it is executing a main program (SALF off) or a [[subroutine]] (SALF on). For a main program, the T field of an Operand Call or Descriptor Call syllable is relative to the Program Reference Table (PRT). For subroutines, the type of addressing is dependent on the high three bits of T and on the Mark Stack [[Flip-flop (electronics)|FlipFlop]] (MSFF), as shown in [[#RelativeAddressing|B5x00 Relative Addressing]].

{| class="wikitable"
|+{{Anchor|RelativeAddressing}}B5x00 Relative Addressing<ref>Taken from {{cite book
 |     series = Systems Documentation
 |      title = Burroughs B5500 Information Processing Systems Reference Manual
 |    section = Table 5-1 Relative Addressing Table
 |  publisher = Burroughs Corporation
 |       date = May 1967
 |        url = http://bitsavers.org/pdf/burroughs/LargeSystems/B5000_5500_5700/1021326_B5500_RefMan_May67.pdf
 |         id = 1021326
 |       page = 5{{hyphen}}4
 }}</ref>
|-
! scope="col" style="text-align: left;" | SALF{{efn|name=SALF}}
! scope="col" style="text-align: left;" | T0<br />A38
! scope="col" style="text-align: left;" | T1<br />A39
! scope="col" style="text-align: left;" | T2<br />A40
! scope="col" style="text-align: left;" | MSFF{{efn|name=MSFF}}
! scope="col" style="text-align: left;" | Base
! scope="col" style="text-align: left;" | Contents
! scope="col" style="text-align: left;" | Index<br />Sign
! scope="col" style="text-align: right;" | Index<br />Bits{{efn|name=IxB}}
! scope="col" style="text-align: right;" | Max<br />Index
|-
| style="text-align: left;"    {{na|text=OFF}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"  | R
| style="text-align: left;"  | Address of PRT
| style="text-align: left;"  | +
| style="text-align: right;" | T 0-9<br />A 38-47
| style="text-align: right;" | 1023
|-
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{na|text=OFF}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"  | R
| style="text-align: left;"  | Address of PRT
| style="text-align: left;"  | +
| style="text-align: right;" | T 1-9<br />A 39-47
| style="text-align: right;" | 511
|-
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{na|text=OFF}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"    {{na|text=OFF}}
| style="text-align: left;"  | F
| style="text-align: left;"  | Address of last RCW{{efn|name=RCW}} or MSCW{{efn|name=MSCW}} on stack
| style="text-align: left;"  | +
| style="text-align: right;" | T 2-9<br />A 40-47
| style="text-align: right;" | 255
|-
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{na|text=OFF}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"  | (R+7){{efn|name=Rp7}}
| style="text-align: left;"  | F register from MSCW{{efn|name=MSCW}} at PRT+7
| style="text-align: left;"  | +
| style="text-align: right;" | T 2-9<br />A 40-47
| style="text-align: right;" | 255
|-
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{na|text=OFF}}
| style="text-align: left;"    {{sdash}}
| style="text-align: left;"  | C{{efn|name=Cf}}
| style="text-align: left;"  | Address of current instruction word
| style="text-align: left;"  | +
| style="text-align: right;" | T 3-9<br />A 41-47
| style="text-align: right;" | 127
|-
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{na|text=OFF}}
| style="text-align: left;"  | F
| style="text-align: left;"  | Address of last RCW{{efn|name=RCW}} or MSCW{{efn|name=MSCW}} on stack
| style="text-align: left;"    {{sdash}}
| style="text-align: right;" | T 3-9<br />A 41-47
| style="text-align: right;"  | 127
|-
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"    {{ya|text=ON}}
| style="text-align: left;"  | (R+7){{efn|name=Rp7}}
| style="text-align: left;"  | F register from MSCW{{efn|name=MSCW}} at PRT+7
| style="text-align: left;"    {{sdash}}
| style="text-align: right;" | T 3-9<br />A 41-47
| style="text-align: right;" | 127
|-
| scope=row colspan='11' | '''Notes:'''<br />{{Notelist|2|refs=
{{efn | name=Cf   | '''C''' (current [[instruction word]])-relative forced to R (PRT)-relative for Store, Program and I/O Release operators}}
{{efn | name=MSCW | '''MSCW''' Mark Stack Control Word}}
{{efn | name=MSFF | '''MSFF''' Mark Stack FlipFlop}}
{{efn | name=Rp7  | '''F''' register from MSCW at PRT+7}}
{{efn | name=IxB  | For Operand Call (OPDC) and Descriptor Call (DESC) syllables, the relative address is bits 0-9 (T register) of the syllable. For Store operators (CID, CND, ISD, ISN, STD, STN), the A register (top of stack) contains an absolute address if the [[Flag bit]] is set and a relative address if the Flag bit is off.}}
{{efn | name=RCW  | '''RCW'''&nbsp; Return Control Word}}
{{efn | name=SALF | '''SALF''' Subroutine Level Flipflop}}
}}
|}