Editing CDC Cyber (section)

===Cyber 200 series===
In 1974, CDC introduced the [[CDC STAR-100|STAR]] architecture.  The STAR is an entirely new 64-bit design with [[virtual memory]] and [[vector processor|vector processing]] instructions added for high performance on a certain class of math tasks.  The STAR's vector pipeline is a ''memory to memory'' pipe, which supports vector lengths of up to 65,536 elements. The latencies of the vector pipeline are very long, so peak speed is approached only when very long vectors are used.  The scalar processor was deliberately simplified to provide room for the vector processor and is relatively slow in comparison to the [[CDC 7600]]. As such, the original STAR proved to be a great disappointment when it was released (see [[Amdahl's Law]]). Best estimates claim that three STAR-100 systems were delivered.

It appeared that all of the problems in the STAR were solvable. In the late 1970s, CDC addressed some of these issues with the ''Cyber 203''. The new name kept with their new branding, and perhaps to distance itself from the STAR's failure. The Cyber 203 contains redesigned scalar processing and loosely coupled I/O design,{{efn|Compared to the tightly coupled I/O used on previous designs.}} but retains the STAR's vector pipeline. Best estimates claim that two Cyber 203s were delivered or upgraded from STAR-100s.

In 1980, the successor to the Cyber 203, the ''Cyber 205'' was announced.<ref>{{cite book |first1=R. W. |last1=Hockney |first2=C. R. |last2=Jesshope |year=1988 |title=Parallel Computers 2: Architecture, Programming and Algorithms |publisher=Adam Hilger |location=Philadelphia |pages=155–185 |isbn=0852748116 }}</ref> The UK [[Meteorological Office]] at [[Bracknell]], England was the first customer and they received their Cyber 205 in 1981. The Cyber 205 replaces the STAR vector pipeline with redesigned vector pipelines: both scalar and vector units utilized [[Emitter-coupled logic|ECL]] [[gate array]] ICs and are cooled with [[Freon]]. Cyber 205 systems were available with two or four vector pipelines, with the four-pipe version theoretically delivering 400 64-bit MFLOPs and 800 32-bit MFLOPs.  These speeds are rarely seen in practice other than by handcrafted [[assembly language]]. The ECL gate array ICs contain 168 logic gates each,<ref>{{cite journal |first=N. R. |last=Lincoln |title=Technology and Design Tradeoffs in the Creation of a Modern Supercomputer |journal=IEEE Trans. Comput. |volume=C-31 |issue=5 |year=1982 |pages=349–362 |doi=10.1109/TC.1982.1676013 |s2cid=14047755 }}</ref> with the [[clock tree]] networks being tuned by hand-crafted coax length adjustment.  The instruction set would be considered V-[[Complex instruction set computer|CISC]] (very complex instruction set) among modern processors.  Many specialized operations facilitate hardware searches, matrix mathematics, and special instructions that enable decryption.

The original Cyber 205 was renamed to ''Cyber 205 Series 400'' in 1983 when the Cyber 205 Series 600 was introduced. The Series 600 differs in memory technology and packaging but is otherwise the same. A single four-pipe Cyber 205 was installed. All other sites appear to be two-pipe installations with final count to be determined.

The Cyber 205 architecture evolved into the [[ETA10]] as the design team spun off into [[ETA Systems]] in September 1983. A final development was the Cyber 250, which was scheduled for release in 1987 priced at $20 million; it was later renamed the ETA30 after ETA Systems was absorbed back into CDC.

==== CDC CYBER 205 ====
* Architecture: ECL/LSI logic<ref>{{Cite report |last1=Dongarra|first1=J. J.|last2=Duff|first2=I. S.|author3=UKAEA Harwell Lab (UK) Computer Science and Systems Div.) |date=1989-09-01|title=Advanced architecture computers|doi=10.2172/5702408|osti=5702408|url=https://www.osti.gov/biblio/5702408|language=English}}</ref>
** 20 ns cycle time (or 50 MHz)
* Up to 800 Mflops FP32 ans 400 Mflops FP64
* 1, 2, 4, 8 or 16 million 64-bit words with 25.6 or 51.2 Gigabits/second
* 8 I/O ports with up to 16 200 Mbits/second each