Editing Cache (computing) (section)

===Prefetch===
{{main|Cache prefetching}}
{{see|Memory paging#Page replacement techniques}}

On a cache read miss, caches with a ''[[demand paging]] policy'' read the minimum amount from the backing store. A typical demand-paging virtual memory implementation reads one page of virtual memory (often 4&nbsp;KB) from disk into the disk cache in RAM. A typical CPU reads a single L2 cache line of 128&nbsp;bytes from DRAM into the L2 cache, and a single L1 cache line of 64&nbsp;bytes from the L2 cache into the L1 cache.

Caches with a [[prefetch input queue]] or more general ''anticipatory paging policy'' go further—they not only read the data requested, but guess that the next chunk or two of data will soon be required, and so prefetch that data into the cache ahead of time. Anticipatory paging is especially helpful when the backing store has a long latency to read the first chunk and much shorter times to sequentially read the next few chunks, such as [[disk storage]] and DRAM.

A few operating systems go further with a [[loader (computing)|loader]] that always pre-loads the entire executable into RAM. A few caches go even further, not only pre-loading an entire file, but also starting to load other related files that may soon be requested, such as the [[page cache]] associated with a [[prefetcher]] or the [[web cache]] associated with [[link prefetching]].