Editing Classic RISC pipeline (section)

===Execute===
The Execute stage is where the actual computation occurs.  Typically this stage consists of an ALU, and also a bit shifter.  It may also include a multiple cycle multiplier and divider.

The ALU is responsible for performing Boolean operations (and, or, not, nand, nor, xor, xnor) and also for performing integer addition and subtraction.  Besides the result, the ALU typically provides status bits such as whether or not the result was 0, or if an overflow occurred.

The bit shifter is responsible for shift and rotations.

Instructions on these simple RISC machines can be divided into three latency classes according to the type of the operation:

* Register-Register Operation (Single-cycle latency):  Add, subtract, compare, and logical operations. During the execute stage, the two arguments were fed to a simple ALU, which generated the result by the end of the execute stage.
* Memory Reference (Two-cycle latency).  All loads from memory. During the execute stage, the ALU added the two arguments (a register and a constant offset) to produce a virtual address by the end of the cycle.
*[[Cycles per instruction|Multi-cycle Instructions]] (Many cycle latency).  Integer multiply and divide and all [[floating-point]] operations. During the execute stage, the operands to these operations were fed to the multi-cycle multiply/divide unit. The rest of the pipeline was free to continue execution while the multiply/divide unit did its work.  To avoid complicating the writeback stage and issue logic, multicycle instruction wrote their results to a separate set of registers.