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CompactFlash
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====Solid state==== For reads, the onboard controller first powers up the memory chips from standby. Reads are usually in parallel, error correction is done on the data, then transferred through the interface 16 bits at a time. Error checking is required due to soft read errors. Writes require powerup from standby, wear leveling calculation, a block erase of the area to be written to, ECC calculation, write itself (an individual memory cell read takes around 100 ns, a write to the chip takes 1ms+ or 10,000 times longer). Because the USB 2.0 interface is limited to 35 MB/s and lacks bus mastering hardware, USB 2.0 implementation results in slower access. Modern UDMA-7 CompactFlash Cards provide data rates up to 145 MB/s<ref>{{cite web|url=http://pietrzyk.us/media-card-study/|title=UDMA-7/UHS-1 Media Card Study|date=16 August 2013|website=pietrzyk.us|access-date=18 March 2018|archive-url=https://web.archive.org/web/20170211080838/http://pietrzyk.us/media-card-study/|archive-date=11 February 2017|url-status=dead}}</ref> and require USB 3.0 data transfer rates.<ref>{{cite web|url=http://pietrzyk.us/usb-3-0-cf-card-reader-study/|title=USB 3.0 CF Card Reader Study|date=14 August 2013|website=pietrzyk.us|access-date=18 March 2018|archive-url=https://web.archive.org/web/20161229054617/http://pietrzyk.us/usb-3-0-cf-card-reader-study/|archive-date=29 December 2016|url-status=dead}}</ref> A direct motherboard connection is often limited to 33 MB/s because IDE to CF adapters lack high speed ATA (66 MB/s plus) cable support. Power on from sleep/off takes longer than power up from standby.
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