Editing Control unit (section)

== Out of order control units ==

A control unit can be designed to [[Microarchitecture#Out-of-order execution|finish what it can]]. If several instructions can be completed at the same time, the control unit will arrange it. So, the fastest computers can process instructions in a sequence that can vary somewhat, depending on when the operands or instruction destinations become available. Most supercomputers and many PC CPUs use this method. The exact organization of this type of control unit depends on the slowest part of the computer.

When the execution of calculations is the slowest, instructions flow from memory into pieces of electronics called "issue units." An issue unit holds an instruction until both its operands and an execution unit are available. Then, the instruction and its operands are "issued" to an execution unit. The execution unit does the instruction. Then the resulting data is moved into a queue of data to be written back to memory or registers. If the computer has multiple execution units, it can usually do several instructions per clock cycle.

It is common to have specialized execution units. For example, a modestly priced computer might have only one floating-point execution unit, because floating point units are expensive. The same computer might have several integer units, because these are relatively inexpensive, and can do the bulk of instructions.
 
One kind of control unit for issuing uses an array of electronic logic, a "scoreboard"<ref>{{cite book |last1=Thornton |first1=J.E. |title=Design of a Computer: The CDC 6600 |url=https://archive.org/details/designcomputerco6600thor |url-access=limited |date=1970 |publisher=Scott, Foreman and Co. |location=Atlanta |page=[https://archive.org/details/designcomputerco6600thor/page/n134 125]|isbn=9780673059536 }}</ref> that detects when an instruction can be issued. The "height" of the array is the number of execution units, and the "length" and "width" are each the number of sources of operands. When all the items come together, the signals from the operands and execution unit will cross. The logic at this intersection detects that the instruction can work, so the instruction is "issued" to the free execution unit. An alternative style of issuing control unit implements the [[Tomasulo algorithm]], which reorders a hardware queue of instructions. In some sense, both styles utilize a queue. The scoreboard is an alternative way to encode and reorder a queue of instructions, and some designers call it a queue table.<ref name="leighton">{{cite web |last1=Leighton |first1=Luke |title=Libre RISC-V M-Class |url=https://www.crowdsupply.com/libre-risc-v/m-class/updates/modernising-1960s-computer-technology-learning-from-the-cdc-6600 |website=Crowd Supply |access-date=16 January 2020}}</ref><ref name="rv5via6600">{{cite web |last1=Alsup |first1=Mitch |last2=Leighton |first2=Luke |last3=Zaruba |first3=Florian |last4=Thornton |first4=James |last5=Kimmitt |first5=Jonathon |last6=Petrisko |first6=Dan |last7=Takano |first7=S. |last8=Falvo |first8=Samuel |title=RISC-V HW Dev, 6600-style out-of-order scoreboard |url=https://groups.google.com/a/groups.riscv.org/forum/#!msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ |website=Google Groups |publisher=RISC-V Foundation |access-date=16 January 2020}}</ref>

With some additional logic, a scoreboard can compactly combine execution reordering, register renaming and precise exceptions and interrupts. Further it can do this without the power-hungry, complex content-addressable memory used by the Tomasulo algorithm.<ref name="leighton" /><ref name="rv5via6600" />

If the execution is slower than writing the results, the memory write-back queue always has free entries. But what if the memory writes slowly? Or what if the destination register will be used by an "earlier" instruction that has not yet issued? Then the write-back step of the instruction might need to be scheduled. This is sometimes called "retiring" an instruction. In this case, there must be scheduling logic on the back end of execution units. It schedules access to the registers or memory that will get the results.<ref name="leighton" /><ref name="rv5via6600" />

Retiring logic can also be designed into an issuing scoreboard or a Tomasulo queue, by including memory or register access in the issuing logic.<ref name="leighton" /><ref name="rv5via6600" />

Out of order controllers require special design features to handle interrupts. When there are several instructions in progress, it is not clear where in the instruction stream an interrupt occurs. For input and output interrupts, almost any solution works. However, when a computer has virtual memory, an interrupt occurs to indicate that a memory access failed. This memory access must be associated with an exact instruction and an exact processor state, so that the processor's state can be saved and restored by the interrupt. A usual solution preserves copies of registers until a memory access completes.<ref name="leighton" /><ref name="rv5via6600" />

Also, out of order CPUs have even more problems with stalls from branching, because they can complete several instructions per clock cycle, and usually have many instructions in various stages of progress. So, these control units might use all of the solutions used by pipelined processors.<ref name="rv5boomreuse">{{cite web |last1=Celio |first1=Chris |title=BOOM Docs, Rocketship SOC Generator |url=https://docs.boom-core.org/en/latest/sections/intro-overview/rocket-chip.html |access-date=16 January 2020}}</ref>