Editing Coreboot (section)

=== Initializing DRAM ===
The most difficult hardware that coreboot initializes is the [[Memory controller|DRAM controller]]s and [[Dynamic random-access memory|DRAM]]. In some cases, technical documentation on this subject is [[Non-disclosure agreement|NDA]] restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's [[Processor register|general purpose registers]] or Cache-as-RAM as temporary storage.

romcc, a [[C (programming language)|C]] [[compiler]] that uses registers instead of RAM, eases the task. Using romcc, it is relatively easy to make [[System Management Bus|SMBus]] accesses to the [[Serial presence detect|SPD]] ROMs of the DRAM [[DIMM]]s, that allows the RAM to be used.

With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM<ref>{{cite web |url=http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf |title=CAR: Using Cache as RAM in Linux BIOS |date=15 January 2009 |access-date=25 February 2014 |author1=Yinghai Lu |author2=Li-Ta Lo |author3=Gregory R. Watson |author4=Ronald G. Minnich |publisher=qmqm.pl |archive-url=https://web.archive.org/web/20160303223305/http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf |archive-date=3 March 2016 |url-status=dead }}</ref><ref>{{Cite web|url=http://www.coreboot.org/images/6/6c/LBCar.pdf|title=A Framework for Using Processor Cache as RAM (CAR)}}</ref> mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard.

For most modern x86 platforms, closed source binary-only components provided by the vendor are used for DRAM setup.  For Intel systems, FSP-M is required, while AMD has no current support. Binary AGESA is currently used for proprietary UEFI firmware on AMD systems, and this model is expected to carry over to any future AMD-related coreboot support.<ref>{{cite web|url=https://mail.coreboot.org/pipermail/coreboot/2014-November/078892.html|title=[coreboot] AMD's binary-only AGESA libraries|last=Griffith|first=Bruce|date=5 November 2014|access-date=2019-09-08}}</ref>