Editing Cray-3 (section)

==Architecture==

===Logical design===
The Cray-3 system architecture comprised a ''foreground processing system'', up to 16 ''background processors'' and up to 2 gigawords (16 GB) of ''common memory''. The foreground system was dedicated to [[input/output]] and system management. It included a 32-bit processor and four synchronous data channels for [[mass storage]] and network devices, primarily via [[HiPPI]] channels.{{sfn|Brochure|1993|p=6}}

Each background processor consisted of a ''computation section'', a ''control section'' and ''local memory''. The computation section performed [[64-bit]] scalar, [[floating point]] and [[Vector processor|vector arithmetic]]. The control section provided instruction buffers, memory management functions, and a [[real-time clock]]. 16 kilowords (128 kbytes) of high-speed local memory was incorporated into each background processor for use as temporary scratch memory.{{sfn|Brochure|1993|p=4}}

Common memory consisted of silicon [[CMOS]] [[Static Random Access Memory|SRAM]], organized into ''octants'' of 64 banks each, with up to eight octants possible. The [[word size]] was 64-bits plus eight [[error-correction]] bits, and total memory bandwidth was rated at 128 gigabytes per second.{{sfn|Brochure|1993|p=5}}

===CPU design===
[[File:Cray-3 complete module.jpg|right|288px|thumb|Typical module layout, with a 4x4 arrangement of "submodules", stacked 4-deep. The metal connectors on the bottom are power connections.]]

As with previous designs, the core of the Cray-3 consisted of a number of [[Computer module|modules]], each containing several circuit boards packed with parts. In order to increase density, the individual [[GaAs]] chips were not [[Integrated circuit packaging|packaged]], and instead several were mounted directly with ultrasonic gold bonding to a board approximately {{convert|1|inch}} square. The boards were then turned over and mated to a second board carrying the electrical wiring, with wires on this card running through holes to the "bottom" (opposite the chips) side of the chip carrier where they were bonded, hence sandwiching the chip between the two layers of board.  These ''submodules'' were then stacked four-deep and, as in the Cray-2, wired to each other to make a 3D circuit.{{sfn|Lester|1993}}

Unlike the Cray-2, the Cray-3 modules also included [[edge connector]]s. Sixteen such submodules were connected together in a 4×4 array to make a single module measuring {{convert|121 × 107 × 7|mm|in}}. Even with this advanced packaging the circuit density was low even by 1990s standards, at about 96,000 gates per cubic inch.{{sfn|Brochure|1993|p=8}} Modern CPUs offer gate counts of millions per square inch, and the move to 3D circuits was still just being considered {{asof|2017|lc=yes}}.<ref>{{cite magazine |first=Jared |last=Newman |url=http://www.pcworld.com/article/227260/intels_3d_transistor_why_it_matters.html |title=Intel's 3D Transistor: Why It Matters |magazine=PCWorld |date=5 May 2011}}</ref>

Thirty-two such modules were then stacked and wired together with a mass of twisted-pair wires into a single processor. The basic cycle time was 2.11&nbsp;ns, or 474&nbsp;MHz, allowing each processor to reach about 0.948 [[GFLOPS]], and a 16 processor machine a theoretical 15.17 GFLOP. Key to the high performance was the high-speed access to main memory, which allowed each process to burst up to 8 GB/s.<ref>{{cite web |first=Aad |last=van der Steen |url=http://netlib2.cs.utk.edu/benchmark/top500/reports/report94/Architec/node6.html |title=Short Description of Architectures in the TOP500: The Cray Computer Corporation Cray-3 |website= TOP500 |date=14 November 1995 |archive-url=https://web.archive.org/web/20120328110827/http://netlib2.cs.utk.edu/benchmark/top500/reports/report94/Architec/node6.html |archive-date=28 March 2012}}</ref>

===Mechanical design===
[[File:Cray-3 CPU section, 1995, Computer History Museum.jpg|right|288px|thumb|Complete processor "brick". The modules are visible inside, mounted vertically.]]

The modules were held together in an aluminum chassis known as a "brick". The bricks were immersed in liquid [[fluorinert]] for cooling, as in the Cray-2. A four-processor system with 64 memory modules dissipated about 88&nbsp;kW of power.{{sfn|Lester|1993}} The entire four-processor system was about {{convert|20|in|mm}} tall and front-to-back, and a little over {{convert|2|feet}} wide.{{sfn|Brochure|1993|p=15}}

For systems with up to four processors, the processor assembly sat under a translucent bronzed acrylic cover at the top of a cabinet {{convert|42|in|m}} wide, {{convert|28|in|m}} deep and {{convert|50|in|m}} high,{{sfn|Brochure|1993|p=15}} with the memory below it, and then the power supplies and cooling systems on the bottom. Eight and 16-processors system would have been housed in a larger octagonal cabinet. All in all, the Cray-3 was considerably smaller than the Cray-2, itself relatively small compared to other supercomputers.{{sfn|Brochure|1993|p=15}}

In addition to the system cabinet, a Cray-3 system also needed one or two (depending on number of processors) ''system control pods'' (or "C-Pods"), {{convert|52.5|in|m}} square and {{convert|55.3|in|m}} high, containing power and cooling control equipment.{{sfn|Brochure|1993|p=15}}

===System configurations===
The following possible Cray-3 configurations were officially specified:{{sfn|Brochure|1993|p=10}}

{|class="wikitable"
!scope="col"|Name
!scope="col"|CPUs
!scope="col"|Memory (Mwords)
!scope="col"|I/O Modules
|-
!Cray-3/1-256
|1
|256
|1
|-
!Cray-3/2-256
|2
|256
|1
|-
!Cray-3/4-512
|4
|512
|3
|-
!Cray-3/4-1024
|4
|1024
|3
|-
!Cray-3/4-2048
|4
|2048
|3
|-
!Cray-3/8-1024
|8
|1024
|7
|-
!Cray-3/8-2048
|8
|2048
|7
|-
!Cray-3/16-2048
|16
|2048
|15
|-
|}

===Software===

The Cray-3 ran the Colorado Springs Operating System (''CSOS'') which was based upon Cray Research's [[UNICOS]] [[operating system]] version 5.0.
A major difference between CSOS and UNICOS was that CSOS was ported to standard C with all [[Portable C Compiler|PCC]] extensions that were used in UNICOS removed.<ref name=cray-3-soft-intro-manual>{{cite book |title=CRAY-3 Software Introduction Manual |url=http://bitsavers.org/pdf/cray/CRAY-3/3102_CRAY-3_Software_Introduction_Nov91.pdf |publisher=Cray Computer Corporation |date=1991}}</ref>

Much of the software available under the Cray-3 was derived from Cray Research and included for instance the [[X Window System]], vectorizing [[FORTRAN]] and [[C (programming language)|C]] compilers, [[Network File System|NFS]] and a [[TCP/IP]] stack.{{sfn|Brochure|1993|p=14}}<ref name=cray-3-soft-intro-manual/>