Editing Direct digital synthesis (section)

=== Phase noise and jitter ===

The superior close-in [[phase noise]] performance of a DDS stems from the fact that it is a feed-forward system. In a traditional [[phase locked loop]] (PLL), the [[frequency divider]] in the feedback path acts to multiply the phase noise of the reference oscillator and, within the PLL loop bandwidth, impresses this excess noise onto the VCO output. A DDS, on the other hand, reduces the reference clock phase noise by the ratio <math>f_{clk}/f_o</math> because the fractional division of the clock derives its output. Reference clock [[jitter]] translates directly to the output, but this jitter is a smaller percentage of the output period (by the ratio above). Since the maximum output frequency is limited to <math>f_{clk}/2</math>, the output phase noise at close-in offsets is always at least 6&nbsp;dB below the reference clock phase noise.<ref name="AD DDSvPLL"/>

At offsets far removed from the carrier, the phase-noise floor of a DDS is determined by the power sum of the DAC [[Quantization (signal processing)|quantization]] noise floor and the reference clock phase noise floor.