Editing Dynamic random-access memory (section)

=={{Anchor|ROW}}Principles of operation==
[[Image:square array of mosfet cells read.png|thumb|250px|The principles of operation for reading a simple 4 <math>\times</math>4 DRAM array]]
[[Image:DRAM_cell_field_(details).png|thumb|250px|Basic structure of a DRAM cell array]]
DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit. The figure to the right shows a simple example with a four-by-four cell matrix. Some DRAM matrices are many thousands of cells in height and width.<ref>{{cite web
 |url         = http://www.eng.utah.edu/~cs7810/pres/11-7810-12.pdf
 |title       = Lecture 12: DRAM Basics
 |date        = 2011-02-17
 |access-date  = 2015-03-10
 |website     = utah.edu
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20150616050009/http://www.eng.utah.edu/~cs7810/pres/11-7810-12.pdf
 |archive-date = 2015-06-16
}}</ref><ref>{{cite web
 |url         = https://www.cs.princeton.edu/courses/archive/fall04/cos471/lectures/20-Memory.pdf
 |title       = Lecture 20: Memory Technology
 |date        = 2004-11-23
 |access-date  = 2015-03-10
 |author      = David August
 |website     = cs.princeton.edu
 |pages       = 3–5
 |url-status     = dead
 |archive-url  = https://web.archive.org/web/20050519185856/http://www.cs.princeton.edu/courses/archive/fall04/cos471/lectures/20-Memory.pdf
 |archive-date = 2005-05-19
}}</ref>

The long horizontal lines connecting each row are known as word-lines. Each column of cells is composed of two bit-lines, each connected to every other storage cell in the column (the illustration to the right does not include this important detail). They are generally known as the ''+'' and ''−'' bit lines.

A [[sense amplifier]] is essentially a pair of cross-connected [[inverter (logic gate)|inverter]]s between the bit-lines. The first inverter is connected with input from the + bit-line and output to the − bit-line. The second inverter's input is from the − bit-line with output to the + bit-line. This results in [[positive feedback]] which stabilizes after one bit-line is fully at its highest voltage and the other bit-line is at the lowest possible voltage.

===Operations to read a data bit from a DRAM storage cell===
# The sense amplifiers are disconnected.<ref name="Kenner:24,30">{{harvnb|Keeth|Baker|Johnson|Lin|2007|pp=24–30}}</ref>
# The bit-lines are precharged to exactly equal voltages that are in between high and low logic levels (e.g., 0.5&nbsp;V if the two levels are 0 and 1&nbsp;V). The bit-lines are physically symmetrical to keep the capacitance equal, and therefore at this time their voltages are equal.<ref name="Kenner:24,30"/>
# The precharge circuit is switched off. Because the bit-lines are relatively long, they have enough [[capacitance]] to maintain the precharged voltage for a brief time. This is an example of [[dynamic logic (digital logic)|dynamic logic]].<ref name="Kenner:24,30"/>
# The desired row's word-line is then driven high to connect a cell's storage capacitor to its bit-line. This causes the transistor to conduct, transferring [[Electric charge|charge]] from the storage cell to the connected bit-line (if the stored value is 1) or from the connected bit-line to the storage cell (if the stored value is 0). Since the capacitance of the bit-line is typically much higher than the capacitance of the storage cell, the voltage on the bit-line increases very slightly if the storage cell's capacitor is discharged and decreases very slightly if the storage cell is charged (e.g., 0.54 and 0.45&nbsp;V in the two cases). As the other bit-line holds 0.50&nbsp;V there is a small voltage difference between the two twisted bit-lines.<ref name="Kenner:24,30"/>
# The sense amplifiers are now connected to the bit-lines pairs. Positive feedback then occurs from the cross-connected inverters, thereby amplifying the small voltage difference between the odd and even row bit-lines of a particular column until one bit line is fully at the lowest voltage and the other is at the maximum high voltage. Once this has happened, the row is ''open'' (the desired cell data is available).<ref name="Kenner:24,30"/>
# All storage cells in the open row are sensed simultaneously, and the sense amplifier outputs latched. A column address then selects which latch bit to connect to the external data bus. Reads of different columns in the same row can be performed without a [[Memory timings|row opening delay]] because, for the open row, all data has already been sensed and latched.<ref name="Kenner:24,30"/>
# While reading of columns in an open row is occurring, current is flowing back up the bit-lines from the output of the sense amplifiers and recharging the storage cells. This reinforces (i.e. refreshes) the charge in the storage cell by increasing the voltage in the storage capacitor if it was charged to begin with, or by keeping it discharged if it was empty.  Note that due to the length of the bit-lines there is a fairly long propagation delay for the charge to be transferred back to the cell's capacitor. This takes significant time past the end of sense amplification, and thus overlaps with one or more column reads.<ref name="Kenner:24,30"/>
# When done with reading all the columns in the current open row, the word-line is switched off to disconnect the storage cell capacitors (the row is closed) from the bit-lines. The sense amplifier is switched off, and the bit-lines are precharged again.<ref name="Kenner:24,30"/>

===To write to memory===
[[File:Square array of mosfet cells write.png|thumb|250px|right|Writing to a DRAM cell]]

To store data, a row is opened and a given column's sense amplifier is temporarily forced to the desired high or low-voltage state, thus causing the bit-line to charge or discharge the cell storage capacitor to the desired value. Due to the sense amplifier's positive feedback configuration, it will hold a bit-line at stable voltage even after the forcing voltage is removed. During a write to a particular cell, all the columns in a row are sensed simultaneously just as during reading, so although only a single column's storage-cell capacitor charge is changed, the entire row is refreshed (written back in), as illustrated in the figure to the right.<ref name="Kenner:24,30"/>

===Refresh rate===
{{Main|Memory refresh}}
{{See also|#Security}}

Typically, manufacturers specify that each row must be refreshed every 64&nbsp;ms or less, as defined by the [[JEDEC]] standard.

Some systems refresh every row in a burst of activity involving all rows every 64&nbsp;ms. Other systems refresh one row at a time staggered throughout the 64&nbsp;ms interval. For example, a system with 2<sup>13</sup>&nbsp;=&nbsp;8,192 rows would require a staggered [[refresh rate]] of one row every 7.8&nbsp;μs which is 64&nbsp;ms divided by 8,192 rows. A few real-time systems refresh a portion of memory at a time determined by an external timer function that governs the operation of the rest of a system, such as the [[vertical blanking interval]] that occurs every 10–20&nbsp;ms in video equipment.

The row address of the row that will be refreshed next is maintained by external logic or a [[Counter (digital)|counter]] within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct the DRAM to refresh or to provide a row address.

Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.<ref>{{cite journal |url=https://www.usenix.org/legacy/event/sec08/tech/full_papers/halderman/halderman_html/ |title=Lest We Remember: Cold Boot Attacks on Encryption Keys |archive-url=https://web.archive.org/web/20150105103510/https://www.usenix.org/legacy/event/sec08/tech/full_papers/halderman/halderman_html/ |archive-date=2015-01-05 |author=Halderman |display-authors=etal |journal =USENIX Security |date=2008}}</ref>

===Memory timing===
{{Main|Memory timings}}
Many parameters are required to fully describe the timing of DRAM operation. Here are some examples for two timing grades of asynchronous DRAM, from a data sheet published in 1998:<ref name="Micron1">{{cite web|url=http://download.micron.com/pdf/datasheets/dram/d47b.pdf|title=Micron 4 Meg x 4 EDO DRAM data sheet|website=micron.com|access-date=8 May 2018|url-status=dead|archive-url=https://web.archive.org/web/20070927174618/http://download.micron.com/pdf/datasheets/dram/d47b.pdf|archive-date=27 September 2007}}</ref>

{|class="wikitable" style="text-align:center;"
|+ Asynchronous DRAM typical timing
|-
!||"50&nbsp;ns"||"60&nbsp;ns"||Description
|-
|''t''<sub>RC</sub>||84&nbsp;ns||104&nbsp;ns||align=left|Random read or write cycle time (from one full /RAS cycle to another)
|-
|''t''<sub>RAC</sub>||50&nbsp;ns||60&nbsp;ns||align=left|Access time: /RAS low to valid data out
|-
|''t''<sub>RCD</sub>||11&nbsp;ns||14&nbsp;ns||align=left|/RAS low to /CAS low time
|-
|''t''<sub>RAS</sub>||50&nbsp;ns||60&nbsp;ns||align=left|/RAS pulse width (minimum /RAS low time)
|-
|''t''<sub>RP</sub>||30&nbsp;ns||40&nbsp;ns||align=left|/RAS precharge time (minimum /RAS high time)
|-
|''t''<sub>PC</sub>||20&nbsp;ns||25&nbsp;ns||align=left|Page-mode read or write cycle time (/CAS to /CAS)
|-
|''t''<sub>AA</sub>||25&nbsp;ns||30&nbsp;ns||align=left|Access time: Column address valid to valid data out (includes address [[setup time]] before /CAS low)
|-
|''t''<sub>CAC</sub>||13&nbsp;ns||15&nbsp;ns||align=left|Access time: /CAS low to valid data out
|-
|''t''<sub>CAS</sub>||8&nbsp;ns||10&nbsp;ns||align=left|/CAS low pulse width minimum
|}
Thus, the generally quoted number is the /RAS low to valid data out time. This is the time to open a row, settle the sense amplifiers, and deliver the selected column data to the output.  This is also the minimum /RAS low time, which includes the time for the amplified data to be delivered back to recharge the cells. The time to read additional bits from an open page is much less, defined by the /CAS to /CAS cycle time. The quoted number is the clearest way to compare between the performance of different DRAM memories, as it sets the slower limit regardless of the row length or page size. Bigger arrays forcibly result in larger bit line capacitance and longer propagation delays, which cause this time to increase as the sense amplifier settling time is dependent on both the capacitance as well as the propagation latency. This is countered in modern DRAM chips by instead integrating many more complete DRAM arrays within a single chip, to accommodate more capacity without becoming too slow.

When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100&nbsp;MHz state machine (i.e. a 10&nbsp;ns clock), the 50&nbsp;ns DRAM can perform the first read in five clock cycles, and additional reads within the same page every two clock cycles. This was generally described as {{nowrap|"5-2-2-2"}} timing, as bursts of four reads within a page were common.

When describing synchronous memory, timing is described by clock cycle counts separated by hyphens. These numbers represent {{nowrap|''t''<sub>CL</sub>-''t''<sub>RCD</sub>-''t''<sub>RP</sub>-''t''<sub>RAS</sub>}} in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when [[double data rate]] signaling is used. JEDEC standard PC3200 timing is {{nowrap|3-4-4-8}}<ref>{{cite web|title=Corsair CMX1024-3200 (1&nbsp;GByte, two bank unbuffered DDR SDRAM DIMM)|url=http://www.corsairmemory.com/corsair/products/specs/cmx1024-3200.pdf|archive-url=https://web.archive.org/web/20080911032322/http://www.corsairmemory.com/_datasheets/cmx1024-3200.pdf|archive-date=11 September 2008|date=December 2003}}</ref> with a 200&nbsp;MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at {{nowrap|2-2-2-5}} timing.<ref>{{cite web|title=Corsair TWINX1024-3200XL dual-channel memory kit|url=http://www.corsairmemory.com/corsair/products/specs/twinx1024-3200xl.pdf|archive-url=https://web.archive.org/web/20061207112238/http://www.corsairmemory.com/corsair/products/specs/twinx1024-3200xl.pdf|archive-date=7 December 2006|date=May 2004}}</ref>
{|class="wikitable" style="text-align:center;"
|+ Synchronous DRAM typical timing
!rowspan=2 colspan=2| ||colspan=2|PC-3200 (DDR-400)||colspan=2|PC2-6400 (DDR2-800)||colspan=2|PC3-12800 (DDR3-1600)||rowspan=2|Description
|-
!cycles||time||cycles||time||cycles||time
|-
!rowspan=2|''t''<sub>CL</sub>||Typical
|3||15&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns
|rowspan=2 align=left|/CAS low to valid data out (equivalent to ''t''<sub>CAC</sub>)
|-
!Fast
|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns
|-
!rowspan=2|''t''<sub>RCD</sub>||Typical
|4||20&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns
|rowspan=2 align=left|/RAS low to /CAS low time
|-
!Fast
|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns
|-
!rowspan=2|''t''<sub>RP</sub>||Typical
|4||20&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns
|rowspan=2 align=left|/RAS precharge time (minimum precharge to active time)
|-
!Fast
|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns
|-
!rowspan=2|''t''<sub>RAS</sub>||Typical
|8||40&nbsp;ns||16||40&nbsp;ns||27||33.75&nbsp;ns
|rowspan=2 align=left|Row active time (minimum active to precharge time)
|-
!Fast
|5||25&nbsp;ns||12||30&nbsp;ns||24||30&nbsp;ns
|}
Minimum random access time has improved from ''t''<sub>RAC</sub>&nbsp;=&nbsp;50&nbsp;ns to {{nowrap|1=''t''<sub>RCD</sub> + ''t''<sub>CL</sub> = 22.5&nbsp;ns}}, and even the premium 20&nbsp;ns variety is only 2.5 times faster than the asynchronous DRAM. [[CAS latency]] has improved even less, from {{nowrap|1=''t''<sub>CAC</sub> = 13&nbsp;ns}} to 10&nbsp;ns. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25&nbsp;ns {{gaps|(1|600|u=Mword/s)}}, while the EDO DRAM can output one word per ''t''<sub>PC</sub>&nbsp;=&nbsp;20&nbsp;ns (50&nbsp;Mword/s).

====Timing abbreviations====
{|
|
*''t''<sub>CL</sub> – CAS latency
*''t''<sub>CR</sub> – Command rate
*''t''<sub>PTP</sub> – precharge to precharge delay
*''t''<sub>RAS</sub> – RAS active time
*''t''<sub>RCD</sub> – RAS to CAS delay
*''t''<sub>REF</sub> – Refresh period
*''t''<sub>RFC</sub> – Row refresh cycle time
*''t''<sub>RP</sub> – RAS precharge
|
*''t''<sub>RRD</sub> – RAS to RAS delay
*''t''<sub>RTP</sub> – Read to precharge delay
*''t''<sub>RTR</sub> – Read to read delay
*''t''<sub>RTW</sub> – Read to write delay
*''t''<sub>WR</sub> – Write recovery time
*''t''<sub>WTP</sub> – Write to precharge delay
*''t''<sub>WTR</sub> – Write to read delay
*''t''<sub>WTW</sub> – Write to write delay
|}