Editing Hardware description language (section)

== History ==

The first hardware description languages appeared in the late 1960s, looking like more traditional languages.<ref>Barbacci, M. "A comparison of register transfer languages for describing computers and digital systems," Carnegie-Mellon Univ., Dept. of Computer Science, March 1973</ref> The first that had a lasting effect was described in 1971 in [[Gordon Bell|C. Gordon Bell]] and Allen Newell's text ''Computer Structures''.<ref>{{cite book|last1=Bell|first1=C. G.|last2=Newell|first2=A.|title=Computer Structures: Readings and Examples|publisher=McGraw-Hill|year=1971|isbn=0-07-004357-4|url-access=registration|url=https://archive.org/details/computerstructur00bell}}</ref> This text introduced the concept of [[register transfer level]], first used in the ISP language to describe the behavior of the [[Digital Equipment Corporation]] (DEC) [[PDP-8]].<ref>{{cite book|last=Reilly|first=E.D.|title=Milestones in computer science and information technology|url=https://archive.org/details/milestonesincomp0000reil|url-access=registration|page=[https://archive.org/details/milestonesincomp0000reil/page/183 183]|publisher=Greenwood Press|year=2003|isbn=1-57356-521-0}}</ref>

The language became more widespread with the introduction of DEC's PDP-16 RT-Level Modules (RTMs) and a book describing their use.<ref>{{cite book|last1=Bell|first1=C.G.|last2=Grason|first2=J.|last3=Newell|first3=A.|title=Designing Computers and Digital Systems|publisher=Digital Press|year=1972 |lccn=72-89566 |oclc=440245727}}</ref>
At least two implementations of the basic ISP language (ISPL and ISPS) followed.<ref>{{cite report |first1=M.C. |last1=Barbacci |date=1976 |title=The Symbolic Manipulation of Computer Descriptions: ISPL Compiler and Simulator |publisher=Department of Computer Science, Carnegie-Mellon University |doi=10.1184/R1/6610790.v1}}</ref><ref>{{cite report |first1=M.C. |last1=Barbacci |last2=Barnes |first2=G.E. |last3=Cattell |first3=R.G.G. |date=1977 |last4=Siewiorek |first4=D.P. |title=The ISPS Computer Description Language |publisher=Department of Computer Science, Carnegie-Mellon University |doi=10.1184/R1/6610637.v1}}</ref>
ISPS was well suited to describe relations between the [[Input/output|inputs and the outputs]] of the design and was quickly adopted by commercial teams at DEC, and by several research teams in the US and among its allies in the North Atlantic Treaty Organization ([[NATO]]).

The RTM products never succeeded commercially and DEC stopped marketing them in the mid-1980s, as new methods grew more popular, more so [[very-large-scale integration]] (VLSI).

Separate work done about 1979 at the [[University of Kaiserslautern]] produced a language called KARL ("KAiserslautern Register Transfer Language"), which included design calculus language features supporting VLSI chip floorplanning{{technical statement|date=April 2014}} and structured hardware design. This work was also the basis of KARL's interactive graphic sister language ABL, whose name was an [[initialism]] for "a block diagram language".<ref>{{cite report |title=ABL specification |author1=Girardi, G. |author2=Hartenstein, R. |publisher=[[CSELT]] and [[University of Kaiserslautern]] |date=1983}}</ref> ABL was implemented in the early 1980s by the Centro Studi e Laboratori Telecomunicazioni ([[CSELT]]) in Torino, Italy, producing the ABLED graphic VLSI design editor. In the mid-1980s, a VLSI design framework was implemented around KARL and ABL by an international consortium funded by the Commission of the European Union.<ref name=Hartenstein93>{{citation|editor1-first=J.|editor1-last=Mermet|year=2012 |title=Fundamentals and Standards in Hardware Description Languages|publisher=Springer |orig-year=1993 |isbn=9789401119146 |chapter-url=https://books.google.com/books?id=DBrtCAAAQBAJ&pg=PA447 |first1=Reiner W. |last1=Hartenstein |chapter=KARL and ABL |pages=447– |volume=249 |series=NATO Science Series E}}</ref>

By the late 1970s, design using [[programmable logic device]]s (PLDs) became popular, although these designs were primarily limited to designing [[finite-state machine]]s. The work at [[Data General]] in 1980 used these same devices to design the [[Data General Eclipse MV/8000]], and commercial need began to grow for a language that could map well to them. By 1983 [[Data I/O]] introduced ABEL to fill that need.

In 1985, as design shifted to VLSI, [[Gateway Design Automation]] introduced [[Verilog]], and [[Intermetrics]] released the first completed version of the VHSIC Hardware Description Language ([[VHDL]]). VHDL was developed at the behest of the [[United States Department of Defense]]'s [[Very High Speed Integrated Circuit Program]] (VHSIC), and was based on the [[Ada (programming language)|Ada programming language]], and on the experience gained with the earlier development of ISPS.<ref>{{cite report |first1=M.C. |last1=Barbacci |last2=Grout |first2=S. |last3=Lindstrom |first3=G. |last4=Maloney |first4=M.P. |date=1984 |title=Ada as a hardware description language : an initial report |publisher=Department of Computer Science, Carnegie-Mellon University |doi=10.1184/R1/6602984.v1 |citeseerx=10.1.1.938.8003}}</ref> Initially, Verilog and VHDL were used to document and simulate circuit designs already captured and described in another form (such as [[schematic]] files). HDL simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic level, and thus increased design capacity from hundreds of transistors to thousands.{{Citation needed|date=July 2010}} In 1986, with the support of the U.S Department of Defense, [[VHDL]] was sponsored as an [[IEEE standard]] (IEEE Std 1076), and the first IEEE-standardized version of VHDL, IEEE Std 1076-1987, was approved in December 1987. [[Cadence Design Systems]] later acquired Gateway Design Automation for the rights to Verilog-XL, the HDL simulator that would become the de facto standard of [[Verilog simulators]] for the next decade.

The introduction of [[logic synthesis]] for HDLs pushed HDLs from the background into the foreground of digital design. Synthesis tools compiled HDL [[source files]] (written in a constrained format called RTL) into a manufacturable netlist description in terms of [[gate]]s and [[transistor]]s. Writing synthesizable RTL files required practice and discipline on the part of the designer; compared to a traditional schematic layout, synthesized RTL netlists were almost always larger in area and slower in performance{{Citation needed|date=July 2010}}. A circuit design from a skilled engineer, using labor-intensive schematic-capture/hand-layout, would almost always outperform its logically-synthesized equivalent, but the productivity advantage held by synthesis soon displaced digital schematic capture to exactly those areas that were problematic for RTL synthesis: extremely high-speed, low-power, or asynchronous circuitry.

Within a few years, VHDL and Verilog emerged as the dominant HDLs in the electronics industry, while older and less capable HDLs gradually disappeared from use. However, VHDL and Verilog share many of the same limitations, such as being unsuitable for analog or [[Mixed-signal integrated circuit|mixed-signal circuit]] simulation. Specialized HDLs (such as Confluence) were introduced with the explicit goal of fixing specific limitations of Verilog and VHDL, though none were ever intended to replace them.

Over the years, much effort has been invested in improving HDLs. The latest iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces many new features (classes, random variables, and properties/assertions) to address the growing need for better [[test bench]] randomization, design hierarchy, and reuse. A future revision of VHDL is also in development{{when|date=April 2014}}, and is expected to match SystemVerilog's improvements.