Editing Harvard architecture (section)

==Speed==
{{See also|Memory bottleneck|Von Neumann architecture#Von Neumann bottleneck}}

In recent years, the speed of the CPU has grown many times in comparison to the access speed of the main memory. Care needs to be taken to reduce the number of times main memory is accessed in order to maintain performance. If, for instance, every instruction run in the CPU requires an access to memory, the computer gains nothing for increased CPU speed—a problem referred to as being [[memory bound]].

It is possible to make extremely fast memory, but this is only practical for small amounts of memory for cost, power and signal routing reasons. The solution is to provide a small amount of very fast memory known as a [[CPU cache]] which holds recently accessed data. As long as the data that the CPU needs is in the cache, the performance is much higher than it is when the CPU has to get the data from the main memory. On the other side, however, it may still be limited to storing repetitive programs or data and still has a storage size limitation, and other potential problems associated with it.{{efn|As in a well described case of [[Intel 80486]].<ref>{{Cite book |last=Brown |first=John Forrest |url=https://www.worldcat.org/oclc/28966593 |title=Embedded systems programming in C and Assembly |date=1994 |publisher=Van Nostrand Reinhold |isbn=0-442-01817-7 |location=New York |oclc=28966593}}</ref>{{Rp|pages=26-34}}<ref>{{Cite web |title=Embedded Systems Programming: Perils of the PC Cache |url=https://users.ece.cmu.edu/~koopman/pc_cache/espcache.html |archive-url=https://web.archive.org/web/20200115141346/https://users.ece.cmu.edu/~koopman/pc_cache/espcache.html |archive-date=January 15, 2020 |access-date=2022-05-26 |website=users.ece.cmu.edu}}</ref>}}

=== Internal versus external design ===
Modern high performance CPU chip designs incorporate aspects of both Harvard and von Neumann architecture. In particular, the "split cache" version of the [[modified Harvard architecture]] is very common. CPU cache memory is divided into an instruction cache and a data cache. Harvard architecture is used as the CPU accesses the cache. In the case of a cache miss, however, the data is retrieved from the main memory, which is not formally divided into separate instruction and data sections, although it may well have separate memory controllers used for concurrent access to RAM, ROM and (NOR) flash memory.

Thus, while a von Neumann architecture is visible in some contexts, such as when data and code come through the same memory controller, the hardware implementation gains the efficiencies of the Harvard architecture for cache accesses and at least some main memory accesses.

In addition, CPUs often have write buffers which let CPUs proceed after writes to non-cached regions. The von Neumann nature of memory is then visible when instructions are written as data by the CPU and software must ensure that the caches (data and instruction) and write buffer are synchronized before trying to execute those just-written instructions.