Editing In-circuit emulation (section)

==Intel==
To support in-circuit emulator (ICE) debugging on  [[Intel 286]], five additional pins were available on the processor: one input pin to externally force an ICE breakpoint, (<code>ICEBP#</code>) and two alternative pairs of output pins to select operations via the ICE-bus instead of user memory.<ref name="louie-et-al-1984">{{cite patent|number=4547849|country=US|inventor1-first=Glenn|inventor1-last=Louie|inventor2-first=Rafi|inventor2-last=Retter|inventor3-first=Neve|inventor3-last=Shaanan|inventor4-first=James|inventor4-last=Slager|fdate=1984-08-17|pridate=1981-12-09|gdate=1985-10-15|status=patent|url=https://patentimages.storage.googleapis.com/97/6f/f7/5d970cf466267a/US4547849.pdf|title=Interface between a Microprocessor and a Coprocessor|assign1=[[Intel Corporation]]}}<!--|quote=--> "User bus cycle status signals, S1# and S0# support the user's bus and ICE bus cycle status signals, ICES1# and ICES0# support the ICE bus. … The ICE bus is used only for Data Read, Code Read, Halt, Shutdown, and Memory Write cycles. … microprocessor is forced to compatible mode at reset, … it cannot be switched back to compatible mode except by reset (or ICE breakpoint), … ICE must be given special attention since it is the only case in which a switch of the master microprocessor from protection mode to compatibility mode can occur (except for reset). … ICE software begins execution following an ICE breakpoint in compatibility mode and then switches to protection mode for the bulk of its operations."</ref>  On the 80286 two instructions (<code>0F 04</code>, <code>[[LOADALL|0F 05]]</code>) exist to dump/restore the complete CPU state to memory offset 0x800, along with a single-byte override prefix (<code>F1</code>) to enable ICE-mode to access user-memory.