Editing Instruction pipelining (section)

===Hazards===
{{main article|Hazard (computer architecture)}}

The model of sequential execution assumes that each instruction completes before the next one begins; this assumption is not true on a pipelined processor. A situation where the expected result is problematic is known as a [[Hazard (computer architecture)|hazard]]. Imagine the following two register instructions to a hypothetical processor:
 1: add 1 to R5
 2: copy R5 to R6
If the processor has the 5 steps listed in the initial illustration (the 'Basic five-stage pipeline' at the start of the article), instruction 1 would be fetched at time ''t''<sub>1</sub> and its execution would be complete at ''t<sub>5</sub>''. Instruction 2 would be fetched at ''t<sub>2</sub>'' and would be complete at ''t<sub>6</sub>''. The first instruction might deposit the incremented number into R5 as its fifth step (register write back) at ''t<sub>5</sub>''. But the second instruction might get the number from R5 (to copy to R6) in its second step (instruction decode and register fetch) at time ''t<sub>3</sub>''. It seems that the first instruction would not have incremented the value by then. The above code invokes a hazard.

Writing computer programs in a [[compiler|compiled]] language might not raise these concerns, as the compiler could be designed to generate machine code that avoids hazards.

====Workarounds====
In some early DSP and RISC processors, the documentation advises programmers to avoid such dependencies in adjacent and nearly adjacent instructions (called [[delay slot]]s), or declares that the second instruction uses an old value rather than the desired value (in the example above, the processor might counter-intuitively copy the unincremented value), or declares that the value it uses is undefined. The programmer may have unrelated work that the processor can do in the meantime; or, to ensure correct results, the programmer may insert [[NOP (code)|NOP]]s into the code, partly negating the advantages of pipelining.

====Solutions====
Pipelined processors commonly use three techniques to work as expected when the programmer assumes that each instruction completes before the next one begins:
*The pipeline could [[Pipeline stall|stall]], or cease scheduling new instructions until the required values are available. This results in empty slots in the pipeline, or ''bubbles'', in which no work is performed.
*An additional data path can be added that routes a computed value to a future instruction elsewhere in the pipeline before the instruction that produced it has been fully retired, a process called [[operand forwarding]].<ref>{{cite web|url=http://www.csee.umbc.edu/~squire/cs411_l19.html |title=CMSC 411 Lecture 19, Pipelining Data Forwarding |publisher=University of Maryland Baltimore County Computer Science and Electrical Engineering Department |access-date=2020-01-22}}</ref><ref>{{Cite web |url=http://hpc.serc.iisc.ernet.in/~govind/hpc/L10-Pipeline.txt |title=High performance computing, Notes of class 11 |publisher=hpc.serc.iisc.ernet.in |date=September 2000 |access-date=2014-02-08 |url-status=dead |archive-url=https://web.archive.org/web/20131227033204/http://hpc.serc.iisc.ernet.in/~govind/hpc/L10-Pipeline.txt |archive-date=2013-12-27 }}</ref>
*The processor can locate other instructions which are not dependent on the current ones and which can be immediately executed without hazards, an optimization known as [[out-of-order execution]].