Editing Intel 8086 (section)

==Details==
[[File:Intel 8086 pinout.svg|thumb|300px|The 8086 pin assignments in min and max mode]]

===Buses and operation===
All internal registers, as well as internal and external data buses, are 16&nbsp;bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1&nbsp;[[Mebibyte|MiB]] physical address space (2<sup>20</sup> = 1,048,576 x 1 [[byte]]). This address space is addressed by means of internal memory "segmentation". The data bus is [[multiplexed]] with the address bus in order to fit all of the control lines into a standard 40-pin [[dual in-line package]]. It provides a 16-bit I/O address bus, supporting 64&nbsp;[[Kilobyte|KB]] of separate I/O space. The maximum linear address space is limited to 64&nbsp;KB, simply because internal address/index registers are only 16&nbsp;bits wide. Programming over 64&nbsp;KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the [[80386]] architecture introduced wider (32-bit) registers (the memory management hardware in the [[80286]] did not help in this regard, as its registers are still only 16 bits wide).

===Hardware modes of 8086===
Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in ''min'' or ''max'' mode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using an 8087 or 8089 coprocessor. The voltage on pin 33 (MN/{{overline|MX}}) determines the mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus.<ref group="note" >The IBM PC and PC/XT use an Intel 8088 running in maximum mode, which allows the CPU to work with an optional 8087 coprocessor installed in the math coprocessor socket on the PC or PC/XT mainboard. (The PC and PC/XT may require maximum mode for other reasons, such as perhaps to support the DMA controller.)</ref> The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by the 8086 itself.

===Registers and instruction===
{| class="infobox" style="font-size:88%;width:38em;"
|-
|+ Intel 8086 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="21" | '''Main registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| AH
| style="text-align:center;" colspan="8"| AL
| style="background:white; color:black;"| '''[[Accumulator (computing)|AX]]''' (primary accumulator)
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="8"| BH
| style="text-align:center;" colspan="8"| BL
| style="background:white; color:black;"| '''BX''' (base, accumulator)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| CH
| style="text-align:center;" colspan="8"| CL
| style="background:white; color:black;"| '''CX''' (counter, accumulator)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| DH
| style="text-align:center;" colspan="8"| DL
| style="background:white; color:black;"| '''DX''' (accumulator, extended acc)
|-
|colspan="21" | '''Index registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Index register|SI]]
| style="background:white; color:black;"| '''S'''ource '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| DI
| style="background:white; color:black;"| '''D'''estination '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| BP
| style="background:white; color:black;"| '''B'''ase '''P'''ointer
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Stack register|SP]]
| style="background:white; color:black;"| '''S'''tack '''P'''ointer
|-
|colspan="21" | '''Program counter''' <br />
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Program counter|IP]]
| style="background:white; color:black;"| '''I'''nstruction '''P'''ointer
|-
|colspan="21" | '''Segment registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| CS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''C'''ode '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| DS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''D'''ata '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| ES
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''E'''xtra '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| SS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''S'''tack '''S'''egment
|-
|colspan="21" | '''Status register'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| [[Overflow flag|O]]
| style="text-align:center;"| [[Direction flag|D]]
| style="text-align:center;"| [[IF (x86 flag)|I]]
| style="text-align:center;"| [[Trap flag|T]]
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Adjust flag|A]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | Flags
|}
|}
The 8086 has eight more-or-less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.

Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time.

The degree of generality of most registers is much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary [[minicomputer]]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the [[PDP-11]], [[VAX]], [[68000]], [[32016]], etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6800|6800]], [[6809]], [[Intel 8085|8085]], [[MCS-48]], [[Intel 8051|8051]], and other contemporary accumulator-based machines, it is significantly easier to construct an efficient [[code generation (compiler)|code generator]] for the 8086 architecture.

Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and [[PL/M]]; some of the more useful instructions are <code>'''push''' ''mem-op''</code>, and '''ret''' ''size'', supporting the "Pascal [[calling convention]]" directly. (Several others, such as <code>'''push'''&nbsp;''immed''</code> and <code>'''enter'''</code>, were added in the subsequent 80186, 80286, and 80386 processors.)

A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported in [[computer hardware|hardware]]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address (computing)|return address]]es.

The 8086 has 64&nbsp;K of 8-bit (or alternatively 32&nbsp;K of 16-bit word) [[I/O port]] space.

===Flags===
The 8086 has a 16-bit [[status register|flags register]]. Nine of these condition code flags are active, and indicate the current state of the processor: [[Carry flag]] (CF), [[Parity flag]] (PF), [[Auxiliary flag|Auxiliary carry flag]] (AF), [[Zero flag]] (ZF), [[Sign flag]] (SF), [[Trap flag]] (TF), [[IF (x86 flag)|Interrupt flag]] (IF), [[Direction flag]] (DF), and [[Overflow flag]] (OF).
Also referred to as the status word, the layout of the flags register is as follows:<ref>{{Cite book |title=IAPX 86, 88, 186, and 188 user's manual : programmer's reference |author=Intel Corporation |year=1983 |isbn=978-0835930352 |oclc=11091251 |pages=3–5|publisher=Intel }}</ref>
{| class="wikitable"
! Bit
| 15-12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|-
! Flag
| &nbsp;
| OF
| DF
| IF
| TF
| SF
| ZF
| &nbsp;
| AF
| &nbsp;
| PF
| &nbsp;
| CF
|}
===Segmentation===
{{See also|x86 memory segmentation}}
There are also four 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, any external address could be referred to by up to 2<sup>12</sup> = 4096 different segment:offset pairs.<ref>{{cite web |last1=Sedory |first1=Daniel B|title=The Segment:Offset Addressing Scheme |url=https://thestarman.pcministry.com/asm/debug/Segments.html |website=thestarman.pcministry.com |access-date=6 March 2025}}</ref>

{| style="margin-left:5em"
|-
| <code>&nbsp; </code><code style="background:#DED">0110 1000 1000 0111</code><code>0000</code>
| '''Segment''',
| 16 bits, shifted 4 bits left (or multiplied by 0x10)
|-
| <code>+ &nbsp;&nbsp;&nbsp;&nbsp; </code><code style="background:#DDF">1011 0100 1010 1001</code>
| '''Offset''',
| 16 bits
|- style="text-decoration:line-through"
| <code>&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</code>
|
|-
| <code>&nbsp; </code><code style="background:#FDF">0111 0011 1101 0001 1001</code>
| '''Address''',
| 20 bits
|}

Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64&nbsp;KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for [[Relocation (computing)|relocation]], with at most 15&nbsp;bytes of alignment waste.

Compilers for the 8086 family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address.

To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]'' files for instance. Precompiled libraries often come in several versions compiled for different memory models.

According to Morse et al.,.<ref>{{cite journal |first1=Stephen P. |last1=Morse |first2=Bruce W |last2=Ravenel |first3=Stanley |last3=Mazor |first4=William B. |last4=Pohlman |title=Intel Microprocessors: 8008 to 8086 |journal=IEEE Computer |volume=13 |issue=10 |pages=42–60 |date=October 1980 |doi=10.1109/MC.1980.1653375 |s2cid=206445851 |url=https://stevemorse.org/8086history/8086history.doc|url-access=subscription }}</ref> the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16&nbsp;MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1&nbsp;MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins.

In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref group="note" >Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way.

The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of the instruction stream to be queued while waiting for decoding and execution. The queue acts as a First-In-First-Out (FIFO) buffer, from which the Execution Unit (EU) extracts instruction bytes as required. Whenever there is space for at least two bytes in the queue, the BIU will attempt a word fetch memory cycle. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.<ref name="8086Datasheet">{{cite web |title=8086 16-BIT HMOS Processor datasheet |url=https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf |publisher=Intel |access-date=26 November 2021 |archive-date=26 November 2021 |archive-url=https://web.archive.org/web/20211126175101/https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf |url-status=dead }}</ref>

====Porting older software====
Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows [[8-bit computing|8-bit]] software to be quite easily ported to the 8086. The authors of most [[DOS]] implementations took advantage of this by providing an [[Application Programming Interface]] very similar to [[CP/M]] as well as including the simple ''.com'' executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform.