Editing Intel MCS-51 (section)

== Memory architecture ==
The MCS-51 has four distinct types of memory: internal RAM, special function registers, program memory, and external data memory. To access these efficiently, some compilers<ref name="keil">{{cite book |title=Keil C51 Users' Manual |date=2021 |publisher=Keil, a division of ARM Inc. |url=https://www.keil.com/c51/man/c51.htm |access-date=17 May 2021}}</ref> utilize as many as 7 types of memory definitions: internal RAM, single-bit access to internal RAM, special function registers, single-bit access to selected (divisible by 8) special function registers, program RAM, external RAM accessed using a register indirect access, using one of the standard 8-bit registers, and register indirect external RAM access utilizing the 16-bit indirect access register.

The 8051's instruction set is designed as a [[Harvard architecture]] with segregated memory (data and instructions); it can only execute code fetched from program memory and has no instructions to write to program memory. However, the bus leaving the IC has a single address and data path, and strongly resembles a [[von&nbsp;Neumann architecture]] bus.

Most 8051 systems respect the instruction set and require customized features to download new executable programs, e.g. in flash memory.

=== Internal RAM ===
[[Internal RAM]] (IRAM) has an 8-bit address space, using addresses 0 through 0xFF. IRAM from 0x00 to 0x7F contains 128 directly addressable 1-byte registers, which can be accessed using an 8-bit absolute address that is part of the instruction. Alternatively, IRAM can be accessed indirectly: the address is loaded into R0 or R1, and the memory is accessed using the <code>@R0</code> or <code>@R1</code> syntax, or as stack memory through the stack pointer SP, with the <code>PUSH</code>/<code>POP</code> and <code>*CALL</code>/<code>RET</code> operations.

The original 8051 has only 128 bytes of IRAM. The 8052 added IRAM from 0x80 to 0xFF, which can ''only'' be accessed indirectly (e.g. for use as stack space). Most 8051 clones also have a full 256 bytes of IRAM.

Direct accesses to the IRAM addresses 0x80–0xFF are, instead, mapped onto the special function registers (SFR), where the accumulators A, B, carry bit C, and other special registers for control, status, etc., are located.

=== Special function registers ===
Special function registers (SFR) are located in the same address space as IRAM, at addresses 0x80 to 0xFF, and are accessed directly using the same instructions as for the lower half of IRAM. They cannot be accessed indirectly via <code>@R0</code> or <code>@R1</code> or by the stack pointer SP; indirect access to those addresses will access the second half of IRAM instead.

The special function registers (SFR) include the accumulators A (or ACC, at E0) and B (at F0) and program status word (or PSW, at D0), themselves, as well as the 16-bit data pointer DPTR (at 82, as DPL and 83 as DPH). In addition to these, a small core of other special function registers{{snd}} including the interrupt enable IE at A8 and interrupt priority IP at B8; the I/O ports P0 (80), P1 (90), P2 (A0), P3 (B0); the serial I/O control SCON (98) and buffer SBUF (99); the CPU/power control register PCON (87); and the registers for timers 0 and 1 control (TCON at 88) and operation mode (TMOD at 89), the 16-bit timer 0 (TL0 at 8A, TH0 at 8C) and timer 1 (TL1 at 8B, TH1 at 8D){{snd}} are present on all versions of the 8051. Other addresses are version-dependent; in particular, the registers of timer&nbsp;2 for the 8052, the control register T2CON (at C8), the 16-bit capture/latch (RCAP2L at CA, RCAP2H at CB) and timer&nbsp;2 (TL2 at CC and TH2 at CD) are not included with the 8051.

=== Register windows ===
The 32 bytes in IRAM from 0x00 to 0x1F contain space for four 8-byte [[register window]]s, which the eight registers R0–R7 map to. The currently active window is determined by a two-bit address contained in the program status word.

=== Bit registers ===
The 16 bytes (128 bits) at IRAM locations 0x20–0x2F contain space for 128 1-bit registers, which are separately addressable as bit registers 00–7F.

The remaining bit registers, addressed as 80–FF, are mapped onto the 16 special function registers 80, 88, 90, 98,&nbsp;..., F0 and F8 (those whose addresses are multiples of 8), and therefore include the bits comprising the accumulators A, B and program status word PSW. The register window address, being bits 3 and 4 of the PSW, is itself addressable as bit registers D3 and D4 respectively; while the carry bit C (or CY), at bit 7 of the PSW, is addressable as bit register D7.

=== Program memory ===
Program memory (PMEM, though less common in usage than IRAM and XRAM) is up to 64&nbsp;KB of read-only memory, starting at address 0 in a separate address space. It may be on- or off-chip, depending on the particular model of chip being used. Program memory is read-only, though some variants of the 8051 use on-chip flash memory and provide a method of re-programming the memory in-system or in-application.

In addition to code, it is possible to store read-only data such as [[lookup table]]s in program memory, retrieved by the {{code|lang=asm|MOVC A,@A+DPTR}} or {{code|lang=asm|MOVC A,@A+PC}} instructions. The address is computed as the sum of the 8-bit accumulator and a 16-bit register (PC or DPTR).

Special jump and call instructions ({{code|lang=asm|AJMP}} and {{code|lang=asm|ACALL}}) slightly reduce the size of code that accesses local (within the same 2&nbsp;KB) program memory.<ref>ACALL is a 2-byte subroutine calling instruction, it can access locations within the same 2{{nbsp}}KB segment of memory. The absolute memory address is formed by the high 5 bits of the PC and the 11 bits defined by the instruction.</ref>

When code larger than 64&nbsp;KB is required, a common system makes the code bank-switched, with general-purpose I/O selecting the upper address bits. Some 8051 compilers<ref name="keil"/> make provisions to automatically access paged code. In these systems, the interrupt vectors and paging table are placed in the first 32&nbsp;KB of code and are always resident.

=== External data memory ===
External data memory (XRAM) is a third address space, also starting at address 0, and allowing 16 bits of address space. It can also be on- or off-chip; what makes it "external" is that it must be accessed using the {{code|lang=asm|MOVX}} (move external) instruction. Many variants of the 8051 include the standard 256&nbsp;bytes of IRAM plus a few kilobytes of XRAM on the chip.

The first 256 bytes of XRAM may be accessed using the {{code|lang=asm|MOVX A,@R0}}, {{code|lang=asm|MOVX A,@R1}}, {{code|lang=asm|MOVX @R0,A}}, and {{code|lang=asm|MOVX @R1,A}} instructions. The full 64&nbsp;KB may be accessed using {{code|lang=asm|MOVX A,@DPTR}} and {{code|lang=asm|MOVX @DPTR,A}}. The 16-bit address requires the programmer to load the 16-bit index register. For this reason, RAM accesses with 16-bit addresses are substantially slower.

Some CPUs<ref name="teridian">{{cite web |title=Silergy 71M6513 Data sheet |url=https://www.silergy.com/download/upload/pdffile/71M6513_DS_Rev4.pdf/2673 |website=Silergy electricity metering ICs |publisher=Silergy Corp. |access-date=17 May 2021}}</ref> permit the 8-bit indirect address to use any 8-bit general-purpose register.

To permit the use of this feature, some 8051-compatible microcontrollers with internal RAM larger than 256 bytes, or an inability to access external RAM,<ref name="teridian"/> access internal RAM as if it were external and have a special function register (e.g. PDATA) that permits them to set the upper address of the 256-byte page. This emulates the MCS8051 mode that can page the upper byte of a RAM address by setting the general-purpose I/O pins.

When RAM larger than 64&nbsp;KB is required, a common system makes the RAM bank-switched, with general-purpose I/O selecting the upper address bits. Some 8051 compilers<ref name="keil"/> make provisions to automatically access paged data.