Editing Intel i960 (section)

===80960MC===
The i960MC included all of the features of the original BiiN system; but these were simply not mentioned in the specifications, leading some{{who|date=July 2018}} to wonder why the i960MC was so large and had so many pins - 53 out of 132<ref>{{Cite web |url=http://www.bitsavers.org/components/intel/i960/271080-006_80960MC_Advance_Information_Jan91.pdf |title=80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT |date=1990 |access-date=2023-04-05 |website=Intel |pages=24–29}}</ref> - labeled "no connect". Later iterations of the i960, like the 80960Jx series, have a more typical number of "do no connect" and use more power and ground pins and have additional I/O pins instead.<ref>{{Cite web |url=http://www.bitsavers.org/components/intel/i960/80960JA_Data_Sheet_Mar98.pdf |title=80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR |date=March 1998 |access-date=2023-04-05 |website=Intel |pages=22–25}}</ref> However, these "no connect" pins are actually not connected internally and unrelated to the BiiN feature set - the silicon die inside does not have bond pads for them.<ref>{{Cite web |url=http://www.righto.com/2023/07/the-complex-history-of-intel-i960-risc.html |title=The complex history of the Intel i960 RISC processor |date=2023-07-01 |access-date=2023-07-01 |website= |last=Shirriff |first=Ken |quote=The original i960 chips (KA/KB/MC/XA) have a large number of pins that are not connected (marked NC on the datasheet) [...] checking the datasheets shows that all four chips have the same pinout; there are no pins connected only in the more advanced versions. Second, looking at the packaged chip (below) explains why so many pins are unconnected: much of the chip has no bond pads, so there is nothing to connect the pins to.}}</ref>

The 80960MC contains an on-chip [[memory management unit]] and supports [[Fault tolerance|fault tolerant systems]] in conjunction with Intel's M82965 Bus Extension Unit as well. Both chips meets [[MIL-STD-883|MIL-STD-883C]] standard. Both chips became available in the first quarter of 1989 with the price of US$2400 and US$1700 respectively. Extended temperature samples became available in August 1988 as well.<ref name="Lewnes, Ann 1988, page 2">Lewnes, Ann, "Intel's 80960 & 80376 Standouts in the 32-Bit Crowd", Intel Corporation, Microcomputer Solutions, July/August 1988, page 2</ref>

It contains 32 32-bit registers, a 512 byte instruction cache, a [[Call stack#Structure|stack frame cache]], a high speed 32-bit [[Direct memory access|multiplexed burst bus]], and an interrupt controller.<ref name="Ormsby, Jon 1988, page 9">Ormsby, Jon, Editor, "New Product Focus: Components: Intel Enters The World Of 32-Bit Embedded Control", Intel Corporation, Microcomputer Solutions, May/June 1988, page 9</ref> It also has 256 interrupt vectors and 32 levels of interrupt priority.<ref name="Lewnes, Ann 1988, page 2"/>