Editing Interrupt (section)

====Masking====
To ''mask'' an interrupt is to disable it, so it is deferred{{efn|Typically, interrupt events associated with I/O remain pending until the interrupt is enabled or explicitly cleared, e.g., by the '''Test Pending Interruption''' ('''TPI''') instruction of [[IBM System/370-XA]] and later.}} or ignored{{efn|E.g., when program mask bits on the [[IBM System/360]] are 0 (disabled), the corresponding overflow and significance events do not result in a pending interrupt.}} by the processor, while to ''unmask'' an interrupt is to enable it.<ref>{{cite book|first=Ying|last=Bai|year=2017|page=21|publisher=CRC Press|url=https://books.google.com/books?id=TDENDgAAQBAJ&pg=PA21|title=Microcontroller Engineering with MSP432: Fundamentals and Applications|isbn=978-1-4987-7298-3|lccn=2016020120|quote=In Cortex-M4 system, the interrupts and exceptions have the following properties: ... Generally, a single bit in a mask register is used to mask (disable) or unmask (enable) certain interrupt/exceptions to occur}}</ref>

Processors typically have an internal ''interrupt mask'' register,{{efn|The mask register may be a single register or multiple registers, e.g., bits in the [[Program status word|PSW]] and other bits in [[control register]]s.}} which allows selective enabling<ref name=":0" /> (and disabling) of hardware interrupts. Each interrupt signal is associated with a bit in the mask register. On some systems, the interrupt is enabled when the bit is set, and disabled when the bit is clear. On others, the reverse is true, and a set bit disables the interrupt. When the interrupt is disabled, the associated interrupt signal may be ignored by the processor, or it may remain pending. Signals which are affected by the mask are called ''maskable interrupts''.

Some interrupt signals are not affected by the interrupt mask and therefore cannot be disabled; these are called ''[[non-maskable interrupt]]s'' (NMIs). These indicate high-priority events which cannot be ignored under any circumstances, such as the timeout signal from a [[watchdog timer]]. With regard to [[SPARC]], the Non-Maskable Interrupt (NMI), despite having the highest priority among interrupts, can be prevented from occurring through the use of an interrupt mask.<ref>{{cite web |url=https://docs.rtems.org/releases/rtems-4.11.2/cpu-supplement/sparc.html#interrupt-levels |title=Interrupt Levels |access-date=2023-11-17}}</ref>