Editing Itanium (section)

==== Design and delays: 1994–2001 ====
Merced was designed by a team of 500, which Intel later admitted was too inexperienced, with many recent college graduates. Crawford (Intel) was the chief architect, while Huck (HP) held the second position. Early in the development HP and Intel had a disagreement where Intel wanted more dedicated hardware for more floating-point instructions. HP prevailed upon the discovery of [[Pentium FDIV bug|a floating-point hardware bug]] in Intel's [[Pentium (original)|Pentium]]. When Merced was [[Floorplan (microelectronics)|floorplanned]] for the first time in mid-1996, it turned out to be far too large, "this was a lot worse than anything I'd seen before", said Crawford. The designers had to reduce the complexity (and thus performance) of subsystems, including the x86 unit and cutting the L2 cache to 96 KB.{{Efn|For comparison the 180nm Pentium III Xeon MP had a 2 MB on-die L2 cache.}} Eventually it was agreed that the size target could only be reached by using the [[180 nm]] process instead of the intended [[250 nm process|250 nm]]. Later problems emerged with attempts to speed up the critical paths without disturbing the other circuits' speed. Merced was [[Tape-out|taped out]] on 4 July 1999, and in August Intel produced the first complete test chip.<ref name="gambles"/>

The expectations for Merced waned over time as delays and performance deficiencies emerged, shifting the focus and onus for success onto the HP-led second Itanium design, codenamed ''McKinley''. In July 1997 the switch to the [[180 nm process]] delayed Merced into the second half of 1999.<ref>{{cite web |title=Merced "Will Be Out Late 1999," Says Hewlett-Packard |url=https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1 |agency=Computer Business Review |website=Tech Monitor |date=18 July 1997 |url-status=live |archive-url=https://archive.today/20240213040233/https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1 |archive-date= 13 February 2024 }}</ref> Shortly before the reveal of [[Explicitly parallel instruction computing|EPIC]] at the Microprocessor Forum in October 1997, an analyst of the [[Microprocessor Report]] said that Itanium would "not show the competitive performance until 2001. It will take the second version of the chip for the performance to get shown".<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel late to 64-bit computing |url=https://www.cnet.com/news/intel-late-to-64-bit-computing/ |website=[[CNET]] |date=6 October 1997 |url-status=live |archive-url=https://web.archive.org/web/20220627172827/https://www.cnet.com/tech/tech-industry/intel-late-to-64-bit-computing/ |archive-date= Jun 27, 2022 }}</ref> At the Forum, Intel's [[Fred Pollack]] originated the "wait for McKinley" mantra when he said that it would double the Merced's performance and would "knock your socks off",<ref name="cnet_unveil_epic">{{cite web |last1=Kanellos |first1=Michael |title=Intel, HP unveil EPIC technology |url=https://www.cnet.com/news/intel-hp-unveil-epic-technology/ |website=[[CNET]] |date=14 October 1997 |url-status=live |archive-url=https://web.archive.org/web/20220818183735/https://www.cnet.com/tech/tech-industry/intel-hp-unveil-epic-technology/ |archive-date= Aug 18, 2022 }}</ref><ref>{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/3/ |website=Real World Tech |page=3 |date=27 October 1999 |url-status=live |archive-url=https://web.archive.org/web/20231031163355/https://www.realworldtech.com/hp-intel-itanium/3/ |archive-date= Oct 31, 2023 }}</ref> while using the same 180 nm process as Merced.<ref>{{cite news |last1=Gwennap |first1=Linley |title=Intel, HP Make EPIC Disclosure |url=https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf |work=[[Microprocessor Report]] |volume=11 |issue=14 |date=27 October 1997 |url-status=live |archive-url= https://web.archive.org/web/20231031163335/https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf |archive-date= Oct 31, 2023 }}</ref> Pollack also said that Merced's x86 performance would be lower than the fastest x86 processors, and that x86 would "continue to grow at its historical rates".<ref name="cnet_unveil_epic"/> Intel said that IA-64 won't have much presence in the consumer market for 5 to 10 years.<ref>{{cite news |last1=Corcoran |first1=Elizabeth |title=Chipmakers unveil works in progress |url=https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/ |url-access=subscription |newspaper=[[The Washington Post]] |date=15 October 1997 |url-status=live |archive-url= https://archive.today/20240213044222/https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/|archive-date= 13 February 2024 }}</ref>

Later it was reported that HP's motivation when starting to design McKinley in 1996 was to have more control over the project so as to avoid the issues affecting Merced's performance and schedule.<ref name="zdnet_wait">{{cite web |last1=Robertson |first1=Chiyo |title=Merced: Worth the wait? What of McKinley? |url=https://www.zdnet.com/article/merced-worth-the-wait-what-of-mckinley/ |website=[[ZDNet]] |date=17 March 1999}}</ref><ref>{{cite web |last1=Matsumoto |first1=Craig |title=Intel outlines road to McKinley processor |url=https://www.eetimes.com/intel-outlines-road-to-mckinley-processor/ |website=[[EE Times]] |date=8 October 1998}}</ref> The design team finalized McKinley's project goals in 1997.<ref name="HP_McKinley_wp">{{cite CiteSeerX |title=Inside the Intel Itanium 2 Processor: a Hewlett Packard Technical White Paper |date=17 July 2002 | citeseerx=10.1.1.96.8209 }}</ref> In late May 1998 Merced was delayed to mid-2000, and by August 1998 analysts were questioning its commercial viability, given that McKinley would arrive shortly after with double the performance, as delays were causing Merced to turn into simply a development vehicle for the Itanium ecosystem. The "wait for McKinley" narrative was becoming prevalent.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Is Merced doomed? |url=https://www.cnet.com/tech/tech-industry/is-merced-doomed/ |website=[[CNET]] |date=6 August 1998}}</ref> The same day it was reported that due to the delays, HP would extend its line of PA-RISC [[PA-8000]] series processors from PA-8500 to as far as PA-8900.<ref>{{cite news |title=INTEL'S MERCED COULD BE ECLIPSED BY MCKINLEY FOLLOW-ON |url=https://techmonitor.ai/technology/intels_merced_could_be_eclipsed_by_mckinley_follow_on |newspaper=Tech Monitor |date=6 August 1998}}</ref> In October 1998 HP announced its plans for four more generations of PA-RISC processors, with PA-8900 set to reach 1.2 GHz in 2003.<ref>{{cite web |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=HP has two-pronged chip plan |url=http://cnet.com/news/0-1004-200-334214.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20001203183700/http://cnet.com/news/0-1004-200-334214.html |archive-date=2000-12-03 |date=13 October 1998}}</ref>

By March 1999 some analysts expected Merced to ship in volume only in 2001, but the volume was widely expected to be low as most customers would wait for McKinley.<ref name="zdnet_wait"/> In May 1999, two months before Merced's [[tape-out]], an analyst said that failure to tape-out before July would result in another delay.<ref>{{cite web |last1=Gary |first1=Gregory |title=IA 64 Update: Part 1 of 2 |url=https://www.edn.com/ia-64-update-part-1-of-2/ |website=[[EDN (magazine)|EDN]] |date=3 May 1999}}</ref> In July 1999, upon reports that the first silicon would be made in late August, analysts predicted a delay to late 2000, and came into agreement that Merced would be used chiefly for debugging and testing the IA-64 software. Linley Gwennap of [[Microprocessor Report|MPR]] said of Merced that "at this point, everyone is expecting it's going to be late and slow, and the real advance is going to come from McKinley. What this does is puts a lot more pressure on McKinley and for that team to deliver".<ref name="may_slip">{{cite web |last1=Shankland |first1=Stephen |title=Intel's Merced chip may slip further |url=http://news.cnet.com/news/0-1003-200-344601.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20000605083119/http://news.cnet.com/news/0-1003-200-344601.html |archive-date=2000-06-05 |date=8 July 1999}}</ref> By then, Intel had revealed that Merced would be initially priced at $5000.<ref>{{cite web |last1=Hamblen |first1=Matt |title=Intel: No Forced March to Merced |url=https://books.google.com/books?id=51iIcvzoX-AC&pg=PA61 |website=[[Computerworld]] |date=12 July 1999}}</ref> In August 1999 HP advised some of their customers to skip Merced and wait for McKinley.<ref>{{cite web |last1=Shankland |first1=Stephen |title=HP upgrade path bypasses Merced chip |url=http://news.cnet.com/news/0-1003-200-346220.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20000819022147/http://news.cnet.com/news/0-1003-200-346220.html |archive-date=2000-08-19 |date=19 August 1999}}</ref> By July 2000 HP told the press that the first Itanium systems would be for niche uses, and that "You're not going to put this stuff near your data center for several years."; HP expected its Itanium systems to outsell the PA-RISC systems only in 2005.<ref>{{cite web |last1=Shankland |first1=Stephen |title=HP moves slowly into world of Intel 64-bit processors |url=http://www.news.cnet.com/news/0-1003-200-2241414.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010210011931/http://www.news.cnet.com/news/0-1003-200-2241414.html |archive-date=2001-02-10 |date=11 July 2000}}</ref> The same July Intel told of another delay, due to a [[Stepping level|stepping]] change to fix bugs. Now only "pilot systems" would ship that year, while the general availability was pushed to the "first half of 2001". Server makers had largely forgone spending on the R&D for the Merced-based systems, instead using motherboards or whole servers of Intel's design. To foster a wide ecosystem, by mid-2000 Intel had provided 15,000 Itaniums in 5,000 systems to software developers and hardware designers.<ref>{{cite web |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel pushes back schedule for Itanium chip |url=http://news.cnet.com/news/0-1003-200-2284759.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010413122744/http://news.cnet.com/news/0-1003-200-2284759.html |archive-date=2001-04-13 |date=July 18, 2000}}</ref> In March 2001 Intel said Itanium systems would begin shipping to customers in the second quarter, followed by a broader deployment in the second half of the year. By then even Intel publicly acknowledged that many customers would wait for McKinley.<ref>{{cite web |last1=Shankland |first1=Stephen |title=Intel draws out Itanium arrival |url=http://news.cnet.com/news/0-1003-200-4996738.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010413151817/http://news.cnet.com/news/0-1003-200-4996738.html |archive-date=2001-04-13 |date=1 March 2001}}</ref>
[[Image:Itanium Sales Forecasts edit.png|thumb|right|400px|Itanium Server Sales forecast history<ref name="IDC_chart">{{cite web
 | url=http://www.zdnet.com/pictures/charts-mining-itanium/
 | title=Mining Itanium
 | access-date=March 19, 2007
 | date=December 7, 2005
 | work=CNet News
 | archive-date=June 11, 2018
 | archive-url=https://web.archive.org/web/20180611040452/https://www.zdnet.com/pictures/charts-mining-itanium/
 | url-status=dead
 }}</ref><ref name="IDC 2006">{{cite news
 | url=https://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/
 | title=Analyst firm offers rosy view of Itanium
 | access-date=March 20, 2007
 | last=Shankland
 | first=Stephen
 | date=February 14, 2006
 | publisher=[[CNET|CNET News]]
 | archive-date=June 24, 2016
 | archive-url=https://web.archive.org/web/20160624090721/http://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/
 | url-status=live
 }}</ref>]]