Editing JTAG (section)

=== Boundary scan testing ===
JTAG [[boundary scan]] technology provides access to a number of logic signals of a complex integrated circuit, including the device pins. The signals are represented in the boundary scan register (BSR) accessible via the TAP. This permits testing as well as controlling the states of the signals for testing and debugging. Therefore, both software and hardware (manufacturing) faults may be located and an operating device may be monitored.

When combined with built-in self-test ([[Built-in self-test|BIST]]), the JTAG scan chain enables a low overhead, embedded solution to test an IC for certain static faults (shorts, opens, and logic errors). The scan chain mechanism does not generally help diagnose or test for timing, temperature or other dynamic operational errors that may occur. [[Test case]]s are often provided in standardized formats such as [[Serial Vector Format|SVF]], or its binary sibling XSVF, and used in production tests. The ability to perform such testing on finished boards is an essential part of [[Design For Test]] in today's products, increasing the number of faults that can be found before products ship to customers.